View M21001_9034956.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

210xx-dsh-001-d mindspeed technologies? november 2005 mindspeed proprietary and confidential m21012/m21011/M21001 quad multi-rate cdr (42 mbps - 3.2 gbps) applications ? backplane reach extension sonet oc-48, oc-48 with fec systems and modules fibre channel systems gigabit ethernet systems 10gbase-cx4 systems and modules clock synthesizer the m21012 is a high-performance quad multi-rate clock and data recovery (cdr) array, optimized for multi-lane telecom, and dat acom applications. each ch annel has an indep endent multi-rate cdr capable of operating at data-rates between 42 mbps and 3.2 gbps, allowing maximum flexibility in system design. the m21011 is rate d for operation in the range of 1 gbps to 3.2 gbps. the M21001 is rated for operation in the range of 42 mbps to 800 mbps. aside from the difference in supported signal data-rates, the m21012, m21011, and M21001 are identical. signal conditioning features include input equalization and output pre-emphasis, allowing robust rece ption and transmission of signals to other devices up to 60" away. us er-selectable input interface types allow dc-coupled input to cm l, lvds, and lvpecl. the outputs can also be dc-coupled to cml and lvds . frequency acquisition is accomplished with an external referenc e clock. the built-in frequency synthesizer allows multi-rate opera tion, while operating with a single reference clock. the devic e can be controlled either through hardwired pins or an i 2 c -compatible interface. the hardwired mode eliminates the need for an external micro- controller, while allowing control of the key features of the device. the i 2 c-compatible interface allows complete control of the device fea- tures. functional block diagram adapative input equalization universal input buffer bist transmitter mux bist tx bist rx mux selectable cml, lvds output buffer + pre - emphasis din0 [p/n] din3 [p/n] din1 [p/n] din2 [p/n] bist rx cdr array dout3 [p/n] dout0 [p/n] dout1 [p/n] dout2 [p/n] cout3 [p/n] cout0 [p/n] cout1 [p/n] cout2 [p/n] vddt0/1 vddt2/3 multifunction pin array serial interface/hardwired mode mf [11:0] ctrl_mode [1:0] out_mode [1:0] xjtag_en xloa [3:0] xlol [3:0] x r s t voltage regulator xregu_en refclk [p/n] jtag features m21012 has four independent mult i-rate cdrs capable of running between 42 mbps and 3.2 gbps m21011 has four independent mult i-rate cdrs capable of running between 1 gbps and 3.2 gbps M21001 has four independent mult i-rate cdrs capable of running between 42 mbps and 800 mbps flexible dc-coupled input inte rface to cml, lvpecl, and lvds flexible control through i 2 c-compatible interface or hardwired pins jitter generation 4.5 mui rms, ji tter tolerance 0.625 ui typical signal conditioning features for su perior performance on fr4 trace lengths of up to 60", twinax ial cable lengths of up to 25m typical total power cons umption as low as 400 mw with all channels running built-in pattern generator and rece iver for module and system testing
210xx-dsh-001-d mindspeed technologies? ii mindspeed proprietary and confidential ordering information part number package operating data rate m21012-12 72-terminal, 10mm, mlf 42 mbps - 3.2 gbps m21012g-12 (1) 72-terminal, 10mm, mlf (rohs compliant) 42 mbps - 3.2 gbps m21011-12 72-terminal, 10mm, mlf 1 gbps - 3.2 gbps m21011g-12 (1) 72-terminal, 10mm, mlf (rohs compliant) 1 gbps - 3.2 gbps M21001-12 72-terminal, 10mm, mlf 42 mbps - 800 mbps M21001g-12 (1) 72-terminal, 10mm, mlf (rohs compliant) 42 mbps - 800 mbps notes: 1. the letter ?g? de signator after the part number indicates that the device is rohs-compliant. refer to www.mindspeed.com for a dditional information. 2. m21012, m21011, M21001 are the base device numbers, and -12 is th e device revision number. 3. these devices are shipped in trays. revision history revision level date description d release november 2005 discontinued support for lvpecl output interface. added note about reserved two-wire serial interface addresses 00001xx. updated table 2-1 with absolute maximum ratings for high-speed signal, control, interface, and alarm pins. c release july 2005 added rohs compliant part numbers to the ordering information. table 2-2 note 4 updated to reflect 0 c t a 70 c for f vco > 2.666 ghz. added section 1.2.15 to provide details on supported ambient temperature range as a function of data-rate. included figure ?definition of pre-emphasis levels? in section 1.2.11 inserted eye diagrams in section 1.2.10 showing input equalization performance.
210xx-dsh-001-d mindspeed technologies? iii mindspeed proprietary and confidential table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 detailed feature descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.3 internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.4 high-speed input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2.5 cdr reference frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2.6 multifunction pins overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.2.7 multifunction pins defined for hardwired mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2.8 two-wire serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.2.9 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2.10 input deterministic jitter attenuators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2.11 output pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.12 cdr features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.2.13 multi-rate cdr data-rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.2.14 frequency reference acquisition (fra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.2.15 ambient temperature range limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.2.16 loss of activity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.2.17 built-in self test (bist) overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.2.18 bist test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.2.19 bist receiver (b ist rx) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.2.20 bist transmitter (bist tx) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.2.21 junction temperature monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2.22 ic identification / revision code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.3 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.0 product specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
210xx-dsh-001-d mindspeed technologies? iv mindspeed proprietary and confidential 2.5 cdr performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.6 package drawings and surface m ount assembly details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.7 pcb high-speed design and layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.0 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1 global control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.1.1 global control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.1.2 external reference frequency divider c ontrol (rfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.1.3 master ic reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.1.4 ic electronic identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.1.5 ic revision code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.1.6 built in self-test (bist) receiver ch annel select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 3.1.7 built in self-test (bist) receiver ma in control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.1.8 built in self-test (bist) receiver bi t error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.1.9 built in self-test (bist) transmitte r channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.1.10 built in self-test (bist) transmitter main control regist er. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 3.1.11 built in self-test (bist) transmitter pll loss of lock re gister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 3.1.12 built in self-test (bist) transmitte r pll control register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 3.1.13 built in self-test (bist) transmitte r pll control register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.1.14 built in self-test (bist) transmitte r pll control register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 3.1.15 built in self-test (bist) transmitter 20 bit user programmable pattern . . . . . . . . . . . . . . . . . . . . . . . . .52 3.1.16 built in self-test (bist) transmitte r 16/20 bit user programmable pattern . . . . . . . . . . . . . . . . . . . . . .53 3.1.17 built in self-test (bist) transmitte r 16/20 bit user programmable pattern . . . . . . . . . . . . . . . . . . . . . .53 3.1.18 built in self-test (bist) transmitter alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.1.19 internal junction temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.1.20 internal junction temperature value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 3.1.21 cdr loss of lock register alarm status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.1.22 loss of activity register alarm status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3.2 individual channel/cdr control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.2.1 cdr n control register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 3.2.2 cdr n control register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2.3 cdr n control register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2.4 output buffer control for cdr n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.2.5 output buffer pre-emphasis control for output n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 3.2.6 input equalization control for output n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 3.2.7 cdr n loop bandwidth and data sampling point adjust. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.2.8 cdr n fra lol window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 3.2.9 jitter reduction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 4.0 appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1 glossary of terms/acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 4.2 reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.2.1 external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 4.2.2 mindspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
210xx-dsh-001-d mindspeed technologies? v mindspeed proprietary and confidential list of figures figure 1-1. module application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 1-2. backplane application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 figure 1-3. recommended data and reference clock input coupling ci rcuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 figure 1-4. sts-48 waveform after transmission through 76? of pcb traces (input to m21012) . . . . . . . . . . . . . .10 figure 1-5. sts-48 waveform at m21012 output with inpu t shown in figure 1-4 . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 1-6. definition of pre-emphasis levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 1-7. block diagram of fra mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 1-8. m21012 pinout diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 2-1. data input internal circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 2-2. reference clock input internal circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 2-3. clock to data output skew timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 2-4. jitter tolerance specification mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 2-5. jitter transfer specification mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 2-6. cross-section of mlf package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 2-7. 68-pin package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 2-8. 72-pin package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 2-9. pcb footprint for 72-pin 10 mm mlf package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 2-10. pcb pad extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 2-11. recommended via array for thermal pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 2-12. trace-length matching using serp entine pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 2-13. loop length matching fo r differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
210xx-dsh-001-d mindspeed technologies? vi mindspeed proprietary and confidential list of tables table 1-1. typical avdd_i/o and vddt supp ly levels for different input interfaces . . . . . . . . . . . . . . . . . . . . . . . .5 table 1-2. output interface and level mapping (for both hardwire d and software modes) . . . . . . . . . . . . . . . . . .5 table 1-3. output interface and recommended av dd_i/o range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 1-4. mode select pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 1-5. multifunction pins for hardwired mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 1-6. hardwired data-rates and associated reference clock fr equencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 1-7. multifunction pins for two-wire interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 1-8. multifunction pins for jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 table 1-9. valid input data ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 1-10. reference clock frequency ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 1-11. drd/rfd/vcd settings for different data-rates and refe rence frequencies . . . . . . . . . . . . . . . . . . .15 table 1-12. lol window size and decision time examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 1-13. supported ambient temperature range by data-rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 1-14. bist prbs patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 1-15. bist 8b/10b patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 1-16. junction temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 1-17. power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 1-18. high-speed signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 1-19. control, interface, and alarm pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 2-1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 2-2. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 2-3. dc power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 2-4. two-wire serial interface cmos i/o electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 2-5. universal high-speed (uhs) input electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 2-6. pcml (positive current mode logic) output electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 2-7. lvds (low voltage differential signal) output electrical specifications . . . . . . . . . . . . . . . . . . . . . . .30 table 2-8. input equalization performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 2-9. output pre-emphasis performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 2-10. reference clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 table 2-11. cdr high-speed performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 2-12. cdr alarm performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 3-1. register table summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 3-2. global control (globctrl: address 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 3-3. external reference frequency divider control (rfd) (refclk_ctrl: address 04h) . . . . . . . . . . . . . . . . .46 table 3-4. master ic reset (mast reset: address 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 3-5. ic electronic id (chipc ode: address 06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
210xx-dsh-001-d mindspeed technologies? vii mindspeed proprietary and confidential table 3-6. ic revision code (r evcode: address 07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 3-7. built in self-test (bist) recei ver channel select (bistrx_chsel: address 10h) . . . . . . . . . . . . . . . . .47 table 3-8. built in self-test (bist) receiver main control re gister (bistrx_ctrl: address 11h) . . . . . . . . . . . . .48 table 3-9. built in self-test (bist) recei ver bit error counter (bistrx_error: addr ess 12h) . . . . . . . . . . . . . . . .48 table 3-10. built in self-test (bist) tran smitter channel select (bisttx_chsel: addr ess 14h) . . . . . . . . . . . . . . .49 table 3-11. built in self-test (bist) tran smitter main control register (bisttx_ct rl: address 15h) . . . . . . . . . . .49 table 3-12. built in self-test (bist) tr ansmitter pll loss of lock register (b isttx_lolctrl: addr ess 17h) . . . .50 table 3-13. built in self-test (bist) tr ansmitter pll control regi ster a (bisttx_pll_ctrla: address 18h) . . . . .51 table 3-14. built in self-test (bist) tr ansmitter pll control regi ster b (bisttx_pll_ctrlb: address 19h) . . . . .52 table 3-15. built in self-test (bist) tr ansmitter pll control regi ster c (bisttx_pll_ctrlc: address 1ah) . . . . .52 table 3-16. built in self-test (bist) tran smitter 20 bit user programmable pattern (bist_pattern0: address 1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 3-17. built in self-test (bist) transm itter 16/20 bit user programmable pattern (bist_pattern1: address 1ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 3-18. built in self-test (bist) transm itter 16/20 bit user programmable pattern (bist_pattern2: ad dress 1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 3-19. built in self-test (bist) transm itter alarm (bisttx_alarm: address 1fh) . . . . . . . . . . . . . . . . . . . . . .5 3 table 3-20. internal junction temperature monitor (temp_mon: addr ess 20h) . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 3-21. internal junction temperature va lue (temp_value: address 21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 table 3-22. cdr loss of lock register alarm st atus (alarm_lol: address 30h) . . . . . . . . . . . . . . . . . . . . . . . . .55 table 3-23. loss of activity register alarm status (alarm_loa: a ddress 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 3-24. cdr n control register a (cdr_c trla_n: address m0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 3-25. cdr n control register b (cdr_c trlb_n: address m1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 3-26. cdr n control register c (cdr_c trlc_n: address m2h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 3-27. output buffer control for cdr n (o ut_ctrl_n: address m3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 3-28. output buffer pre-em phasis control for output n (p reemp_ctrl_n: address m4h) . . . . . . . . . . . . . . .58 table 3-29. input equalization cont rol for output n (ineq_ctrl_n: address m5h) . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 3-30. cdr n loop bandwidth and data sampling point adju st (phadj_ctrl_n: address m6h) . . . . . . . . . . .60 table 3-31. cdr n fra lol window control (lol _ctrl_n: address m9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 0 table 3-32. jitter reduction control (jitter_reduc_n: address mah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 table 4-1. acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
210xx-dsh-001-d mindspeed technologies? 1 mindspeed proprietary and confidential 1.0 functional description 1.1 applications backplane reach extension sonet oc-48, oc-48 with fec systems and modules fibre channel systems gigabit ethernet systems 10gbase-cx4 systems and modules clock synthesizer figure 1-1. module application linecard connector rx quad or octal cdr quad or octal cdr tx pmd
functional description 210xx-dsh-001-d mindspeed technologies? 2 mindspeed proprietary and confidential figure 1-2. backplane application backplane linecard connector module #1 module #2 module #3 module #3 switch card connector qcdr #1 qcdr #1 qcdr #2 qcdr #2 single fiber modules
functional description 210xx-dsh-001-d mindspeed technologies? 3 mindspeed proprietary and confidential figure 1-3. recommended data and reference clock input coupling circuitry m21012 vddt (connect to vdd_i/o) dinp dinn 50 ? 50 ? 0.1 f 0.1 f 2 k ? 50 ? refclkp refclkn 50 ? clock input buffer 2 k ? 50 ? 50 ? vdd_i/o 10 k ? 10 k ? data input buffer
functional description 210xx-dsh-001-d mindspeed technologies? 4 mindspeed proprietary and confidential 1.2 detailed feature descriptions 1.2.1 conventions throughout this data sheet, phys ical pins will be denoted in bold italic print. an array of pins can be called by each individual pin name (e.g. mf0 , mf1 , mf2 , mf3 , and mf6 ) or as an array (e.g. mf [6,3:0]). the m21012 control is accessed through registers that employ an 8-bit address and an 8-bit data scheme. registers are denoted in italic print, (e.g. testregister) and individual bits within the register will be called out as testregister [4:3] to denote the 4 th and 3 rd bit where bit 0 is the lsb and bit 7 is the msb. many features of the device are bit mapped within a reg - ister; if the status of the other bits are uncertain, it is recommended that the user reads the value from the register before writing, to assure only the desired bits change. writing in the same value to the bits within a register does not cause glitches to the unchanged features. the addresses for the registers as well as their functions can be found in detail in chapter 3.0 . the purpose of the text description is to highlight the features of the registers. for redundant items, such as the channel number, the registers will have a nomenclature of te s t r e g _ 0 for channel 0, te s t r e g _ 1 for channel 1, te s t r e g _ 2 for channel 2, testreg_ 3 for channel 3. for general reference, the text will denote such registers as testreg_ n where n can vary from 0 to 3. individual cdr and loa circuits are mapped to input channels. 1.2.2 reset upon application of power, the m21012 automatically generates a master reset. at any time, forcing xrst = l causes the m21012 to enter the master reset state. a master reset can also be initiated through the registers in the two-wire interface control mode by writing aah to mastreset . once a master reset is in itiated, all registers are returned to the default values, the internal state machines cleared, and all cdr/bist reset to the out-of-lock condi - tion. after a reset, the register mastreset will automatically return to the default value of 00h. each individual cdr can be soft reset by setting cdr_ctrla_ n [7] = 1 where n = 0 for cdr 0, n = 1 for cdr 1 and so on. the bit should be returned to 0b for normal operation. after a soft reset, the registers that determine the cdr operation options such as data-rate, window sizes, etc., remain unchanged and only the cdr state-machine is reset, resulting in an out-of lock condition. 1.2.3 internal voltage regulator the digital and analog core are designed to run at 1.2v, however, for operation from 1.8v to 3.3v, an internal linear voltage regulato r is provided. xregu_en = l enables the voltage regulator which uses avdd_i/o and dvdd_i/o to generate the required 1.2v for avdd_core and dvdd_core . in this mode, the avdd_core and dvdd_core pins should be connected to a floating dc low inductance pcb plane and ac bypassed to vss using standard decou - pling techniques. if desired, avdd_core and dvdd_core can be separated into individual planes. if 1.2v is avail - able, it can be connected directly to avdd_core and dvdd_core, to save power, by bypassing the internal linear regulator with xregu_en = h. in this case, it is recommended that the avdd_core and dvdd_core pins be tied together to a common pcb plane, and bypassed to vss with standard decoupling techniques. 1.2.4 high-speed input/output pins the high-speed input data interface is universal high-speed (uhs), which can support pcml, lvds, and lvpecl with no external components (dc coupled), while 5v pecl or ?5.2v ecl would require ac coupling capacitors (internal 50 ? input pull-ups). the high-speed serial differential da ta (42 mbps to 3200 mbps) enters the device via din [3:0,p/n]. inputs 0 and 1 are internally terminated with 50 ? to vddt0/1 and inputs 2 and 3 are terminated with 50 ? to vddt2/3 . for different applications vddt may be terminated to other dc voltages to minimize dc currents.
functional description 210xx-dsh-001-d mindspeed technologies? 5 mindspeed proprietary and confidential for other input interfaces, dc coupling is permitted if the input level meets the input swing and common-mode requirements by terminating vddt to a dc voltage that keeps the dc curren t draw within specifications. if this dc voltage is not readily available, vddt can be decoupled to ground with high frequency capacitors. in all cases, vddt must be a low-impedance node since it is shared between inputs, which requires either a low impedance plane or bypass capacitors. the m21012 supports multiple high-speed output modes. the output modes are selectable with hardwired pins only. the i/o interface is set with out_mode [1:0] and the output level with mf [9:8] as shown in ta bl e 1-2 . in the two-wire interface mode, the out_ctrl_ n [7:6] register is used to set the data level, and out_mode [1:0] is used to set the interface type. in the two-wire interface mode, the data output can be enabled with out_ctrl_ n [2] = 1b (default) and the output data polarity can be flipped by setting out_ctrl_ n [3] = 1b (default: no inversion). output data polarity flip is an internal function that would have the same effect as switching the p and n terminals. the recommended avdd_i/o for the different output interfaces is shown in ta b l e 1-3 . the pcml+ mode is the same as the pcml mode except that higher output swing levels are provided for applications that may require them. table 1-1. typical avdd_i/o and vddt supply levels for different input interfaces interface logic high range (v) common mode range (v) logic swing range (mvpp diff) avdd_i/o range (v) vddt supply pcml avdd_i/o avdd_i/o - swing/2 100 - 2000 1.8 - 3.3 avdd_i/o lvds 1.4 1.2 100 - 700 1.8 - 3.3 decoupled ac-coupled n/a n/a 100 - 2000 1.8 - 3.3 avdd_i/o note: table for standard interfacing applications. no n-standard interfacing applications must meet i/o specifications. table 1-2. output interface and level mapping (for both hardwired and software modes) multifunction pins & register mf [9:8] out_ctrl_ n [7:6] pcml mode out_mode [1:0] = 00b lvds mode out_mode [1:0] = 01b pcml+ mode out_mode [1:0] = 11b 00b off off off 01b 600 mv rrl at 450 mv 1000 mv 10b 1000 mv gpl at 650 mv 1300 mv 11b 1300 mv 1000 mv 1600 mv table 1-3. output interface and recommended avdd_i/o range output logic avdd_i/o range (v) off 1.8 - 3.3 pcml at 600 mv 1.8 - 3.3 pcml at 1v 1.8 - 3.3 pcml at 1.3v 1.8 - 3.3 pcml+ at 1.6v 1.8 - 3.3 lvds gpl 1.8 - 3.3 lvds rrl 1.8 - 3.3
functional description 210xx-dsh-001-d mindspeed technologies? 6 mindspeed proprietary and confidential 1.2.5 cdr reference frequency the cdr frequency acquisition requires the use of an exte rnal reference clock. an external reference clock is applied to refclk [p/n] to enable frequency reference acquisition (fra) in the cdr. pcml, cmos are examples of the wide variety of interfaces supported for the reference clock. the inputs contain a dc-coupled 100 ? differen - tial termination between refclkp and refclkn along with a 100 k ? pull-down on each terminal to vss . after this termination/pull-down block, the inputs are ac coupled internally. the common-mode and allowable voltage swings are specified in ta bl e 2-10 . the refclk common-mode must be above 250 mv, which may require external pull- ups. 1.2.6 multifunction pins overview the m21012 is designed to be an extremely versatile device, with many user selectable options in the cdr and i/ o, to optimize performance. all of these options can be accessed and controlled through the i 2 c-compatible two- wire serial interface. the i 2 c-compatible serial interface i/o pins and address pins are mapped to the multifunction pins mf [11:0]. a subset of the key features for most applications, such as standard data-rates, i/o levels, etc., can be selected through mf [11:0] in the hardwired mode. the hardwired mode does not require the use of a serial interface. in this mode, upon power up (auto reset on power up), the m21012 function is determined by the status of the hardwired pins. during operation, the hardwired pi ns can change states, which would cause the cdr to fol - low with the appropriate action. another feature of the multifunction pins is to support jtag testing of this device during pcb manufacturing. the various control and test modes of this device are selected with three pins: ctrl_mode [1:0] , and xjtag_en . xjtag_en = l overrides ctrl_mode [1:0] , and puts the device in jtag test mode, while xjtag_en = h allows ctrl_mode [1:0] to determine the m21012 control mode, as summarized in ta b l e 1-4 . table 1-4. mode select pins pin jtag test mode hardwired mode two-wire serial mode xjtag_en l h h ctrl_mode [1:0] no impact 11b 01b
functional description 210xx-dsh-001-d mindspeed technologies? 7 mindspeed proprietary and confidential 1.2.7 multifunction pins de fined for hardwired mode in the hardwired mode, a subset of options in the m21012 can be accessed with hardwired physical pins, as defined in ta bl e 1-5 . the hardwired data-rates along with the default reference clock frequency are shown in ta bl e 1-6 . table 1-5. multifunction pins for hardwired mode pin function description mf0 data-rate selection cdr data-rate select (see table 1-6 for description) mf1 data-rate selection cdr data-rate select (see table 1-6 for description) mf2 data-rate selection cdr data-rate select (see table 1-6 for description) mf3 data-rate selection cdr data-rate select (see table 1-6 for description) mf4 pre-emphasis control l = pre-emphasis enable h = pre-emphasis disable mf5 clock output control l = clock outputs enable h = clock outputs disable mf6 clock polarity flip l = clock polarity flip h = standard clock polarity mf7 data polarity flip l = data polarity flip h = standard data polarity mf8 output level selection 00b: all outputs disabled 01b: 600 mv (cml) 10b: 1v (cml) 11b: 1.3v (cml) see table 1-2 for the other output interface modes. mf9 output level selection mf10 equalization control l = input equalization enabled h = input equalization disabled mf11 cdr bypass control l = all cdrs bypassed and powered down h = all cdrs enabled
functional description 210xx-dsh-001-d mindspeed technologies? 8 mindspeed proprietary and confidential 1.2.8 two-wire serial interface the two-wire serial interface is compatible with the i 2 c standard. the m21012 supports the read/write slave-only mode, 7-bit device address field width, and supports the standard rate of 100 kbps, fast mode of 400 kbps, and high-speed mode of 3.4 mbps. the 7-bit address for the device is determined with mf [6:0], which allows for a max - imum of 124 unique addresses for this device. the four addresses 00001xx (4, 5, 6, 7) are reserved and should not be used. sda ( mf11 ) and scl ( mf10 ) can drive a maximum of 500 pf each at the maximum rate. during the write mode from the master to the m21012, data is latched into the internal m21012 registers on the rising edge of scl, during the acknowledge phase (ack) of communication. ta b l e 1-7 summarizes the multifunction pins for the two-wire serial interface mode. for further information on timing, please see the i 2 c bus specification standard. table 1-6. hardwired data-rates and associated reference clock frequencies pins mf [3:0] application signal data-rate (mbps) reference frequency (mhz) 0000 10x fibre channel - xaui 3187.5 159.375 0001 10 gigabit ethernet - xaui 3125 156.25 0010 sts-48 + fec 2666 19.44 0011 sts-48 2488.32 19.44 0101 2x fibre channel 2125 106.25 0110 gigabit ethernet 1250 125 0111 1x fibre channel 1062.5 106.25 1000 sts-12 622.08 19.44 1001 sts-3 155.52 19.44 1010 sts-1 51.84 19.44 1011 escon 200 10 1100 fe 125 12.5 1101 sts-48 2488.32 155.52 table 1-7. multifunction pins for two-wire interface pin function description mf0 address bit 0 7-bit device address; addr ess bit 0 is lsb, addr ess bit 6 is msb mf1 address bit 1 mf2 address bit 2 mf3 address bit 3 mf4 address bit 4 mf5 address bit 5 mf6 address bit 6 mf10 scl clock input mf11 sda data input/output (open drain)
functional description 210xx-dsh-001-d mindspeed technologies? 9 mindspeed proprietary and confidential 1.2.9 jtag the m21012 supports jtag external boundary scan, which includes all of the high-speed i/o, as well as the tradi - tional digital i/o. ta b l e 1-8 shows the multifunction pins signal mapping for jtag testing. 1.2.10 input determinis tic jitter attenuators each of the four input channels contains an independent input equalizer (ie). for the ie, the address n is mapped to the input channel. in the hardwired mode, there is the option to set input equalization on or off. in the two-wire serial interface control mode, the default state allows for configurable input equalization settings using ineq_ctrl_ n [2:0], for which the setting of 100b is optimized for trace lengths between 10 - 46 inches. the input equalization settings have been optimized for a variety of backplane and connectivity applications, such as board traces and twinaxial cables. for board traces on fr4, such as the tyco electronics hm-zd legacy back - plane, the input equalizer can drive trace-lengths of up to 60? at 3.1875 gbps, and up to 72? at 2.125 gbps. the equalizer has similar high performance on nelco-13, arlon 25, rogers 3003, 4003c, 4340, getek pcb materials, and twinaxial cables. the input equalizer was designed to compensate for the deterministic jitter accumulation effects of typical backplane interconnects, which have bandwidths of hundreds of mhz to a few ghz. the equaliz - ers are not expected to make a significant difference in performance with signal data-rates less than 1 gbps. another component of input deterministic jitter is inter-symbol interference (isi) due to dc offsets. by default, a dc servo-like circuit is enabled to correct for this type of deterministic jitter, and can be disabled by setting ineq_ctrl_ n [4] = 0b. the dc servo can also be used to track changes in the common mode, for single-ended operation. table 1-8. multifunction pins for jtag pin function description mf8 tms test select mf9 tdi test data input mf10 tck test clock mf11 tdo test data output
functional description 210xx-dsh-001-d mindspeed technologies? 10 mindspeed proprietary and confidential figure 1-4. sts-48 waveform after transmission through 76? of pcb traces (input to m21012) figure 1-5. sts-48 waveform at m21012 output with input shown in figure 1-4
functional description 210xx-dsh-001-d mindspeed technologies? 11 mindspeed proprietary and confidential 1.2.11 output pre-emphasis each of the four output channels contains an independent output pre-emphasis circuit that can be used to select the optimal pre-emphasis level. the pre-emphasis settings have been optimized for a variety of backplane and con - nectivity applications. for board traces on fr4, such as the tyco electronics hm-zd legacy backplane, the pre- emphasis circuit can drive trace-lengths of up to 40? at 3.1875 gbps, and up to 60? at 2.125 gbps. like the input equalizer settings, the output pre-emphasis circuit has similar high performance on nelco-13, arlon 25, rogers 3003, 4003c, 4340, getek pcb materials, and twinaxial cables. the digital pre-emphasis level is selected, for each output channel, with preemp_ctrl_ n [2:0], and the default value of 000b corresponds to pre-emphasis dis - abled. the pre-emphasis circuit tracks the signal data-rate throughout the multi-rate range, however, like the input equalizer, it is designed to compensate for the bandwidth limitations of the interconnect, and may not have the desired effects at the low end of the multi-rate range. the output pre-emphasis function is available for all data interfaces and levels. 1.2.12 cdr features the m21012 contains four multi-rate cdrs, that can each operate at independent data-rates. when the cdr achieves phase lock onto the incomi ng data stream, the cdr removes the in coming random jitte r above its loop bandwidth, as well as any deterministi c jitter remaining from the two input de terministic jitter attenuators (ie & dc servo). the m21012 output data has extremely low jitter, due to retiming with a very low jitter generation cdr. the output pre-emphasis option allows for compensation of interconnect deterministic jitter, generated up to the next downstream device. each cdr is capable of multi-rate operation which is achieved by a combination of built in vco frequency dividers (vcd), data rate dividers (drd) , and a wide vco tuning range (f min = 2.0 ghz, f max = 3.2 ghz). as a result, the allowed input data range is f min / drd max to f max / drd min . although the ranges are not continuous, the ranges are deliberately chosen to cover all typical applications. by default, the loop-bandwidth is set to pass sonet sts-48 specifications, with drd = 1 and f vco = 2.48832 ghz, with less than 0.1 db of jitter peaking, and approximate bandwidth of 2 mhz. within a given vco frequency figure 1-6. definition of pre-emphasis levels v b v s pre-emphasis level = x 100 v b v s
functional description 210xx-dsh-001-d mindspeed technologies? 12 mindspeed proprietary and confidential range, the bandwidth will scale proportionately. for example, if the loop bandwidth (f lbw ) is 2 mhz at 2.48332 ghz, then at 3.125 ghz the f lbw will be 2.5 mhz, and peaking will be less than 0.1 db. when drd is not equal to 1, the bandwidth at drd = 1 scales by the drd divide ratio. for example, if the f lbw is 2 mhz at sts-48 with drd = 1, then if drd = 4 for sts-12 operation, the f lbw will be 500 khz. in the hardwired mode, the f lbw will be properly set for the hardwired data-rates. in the two-wire serial interface mode, the default bandwidth scales auto - matically with the input signal data-rate. the loop bandwidth (f lbw ) can also be tuned through the registers. the cdr needs to achieve frequency lock before it can achieve phase lock and re-time the input data. frequency reference acquisition (fra) requires an external frequency source to be connected to the refclk [p/n] pins. frequency acquisition is accomplished with two key sections. the first section is a secondary frequency lock loop (fll) that drives the vco towards the desired frequency. the second section is the loss-of-lock circuitry (lolcir), that turns on or off the secondary fll. both loss of lo ck (lol) and loss of activity (loa) have register bits ( alarm_loa and alarm_lol ) which are active high, and pins ( xloa [3:0] and xlol [3:0]) which are active low. xloa [3:0] and xlol [3:0] can be wired or externally. in general co ntext, they will be referr ed to as lol or loa which is active h. frequency acquisiti on takes place when the lolcir determines an out of lock condition (lol = h) for each cdr, when the vco frequency exceeds a given range (window). the lolcir enables the secondary fll to drive the vco close to the desired frequency (the in put signal data-rate). when the vco falls within a given frequency range where the cdr loop can acquire phase lock, the lolcir turns off the secondary fll and sets lol = l, allowing the cdr to achieve phase lock. during this time, the lolcir continues to monitor the frequency difference and will signal a lol = h, to start the acquisit ion routine again, if the fr equency falls out of range. the lolcir range is fixed in the hardwired mode, and programmable in the two-wire interface mode. the frequency threshold (window) for lol = h-to-l and lol = l-to-h are different, to prevent lol from toggling when the fre - quency is near one of the windows. these registers also control the frequency acquisition time. suggested values are given in this document for general robust operation, and are used as register defaults, however, the program - mability of the registers allow for optimization based on a given app lication (e.g. faster lock times). each cdr contains an independent loss of activity (loa) detector that determines if there is valid data, by compar - ison with the transition density of the reference clock; th is assumes a 50% transition density for the data. fixed win - dow detectors compare the data transition density with the re ference frequency. if the data transition density falls outside of the 50% +/- 12.5% window, a loss of activity cond ition is signaled. when loa goes high, it (just like lol) forces the fll to turn on, so that the vco will be forced to the desired frequency range. when loa goes low again, phase lock will occur. all of the cdrs are reset upon xrst = l, mastreset = aah, or upon power up. a soft reset through cdr_ctrla_ n [7] = 1b resets the individual cdr st ate machine, and presets the cdr to an out-of-lock condition, however, the register contents that are related to cdr setup are unchanged. it is required to force a soft-reset if the signal data- rate is dynamically changed. the soft reset register bit needs to be cleared for proper operation. a reset during operation will cause bit errors, unt il the cdr achieves phase lock. by default, all of the cdrs are active and powered up for normal op eration. by setting cdr_ctrlb_ n [7:6] = 11b, a cdr can be bypassed and powered down, to allow for non-standard data-rates, or to save power when the cdr is not required at lower data-rates. when cdr_ctrlb_ n [7:6] = 01b, the cdr is bypassed but active (vco locked to the input data), the output data is not re-timed. in the last mode with cdr_ctrlb_ n [7:6] = 10b, the cdr is powered down and the input and output paths are also powered down. in this case the input signal does not reach the out - put, so this setting should only be used to power down unused channels. the on-chip loop filter automatically scales with the vco data-rate divider selection. for operation with a fixed drd setting, the loop bandwidth scales proportionally to the new data-rate, from the standard sonet operating fre - quency. from the default setting, the bandwidth can be reduced to 80% with phadj_ctrl_ n [5:4] = 00b, and increased to 400% with phadj_ctrl_ n [5:4] = 10b. to prevent the propagation of noise in the case where there is a lol/loa condition, the cdr contains an auto- inhibit feature, which is enabled by default. when either loa or lol is active, the output of the cdr is fixed at a logic high state ( doutp = h, doutn = l). this feature can be disabled by setting cdr_ctrla_ n [3] = 0b, which allows cdr_ctrla_ n [5] to either force an inhibit (1b) or to never inhibit (0b).
functional description 210xx-dsh-001-d mindspeed technologies? 13 mindspeed proprietary and confidential in some optical module and backplane applications, the optimal data sampling point is not in the middle of the data eye. by default, the cdr achieves phase lock very near th e center of the eye. for optimal performance (jitter toler - ance), the actual sampling point can be adjusted with phadj_ctrl_ n [3:0]. the adjustment range is from ?122.5 mui to +122.5 mui with 17.5 mui steps. 1.2.13 multi-rate cdr data-rate selection for multi-rate operation, the first step is to determine the desired data-rate range. the input data range must be bracketed by df min = f vco,min /drd max to df max = f vco,max /drd min . df max/min are the maximum/minimum input data-rate frequencies, drd max/min are the maximum/minimum data-rate divider settings using cdr_ctrlb_ n [3:0] , and f vco,min /f vco,max are the minimum/maximum vco frequencies, which are 2.0 ghz and 3.2 ghz respectively. the valid data-rates are shown in ta b l e 1-9 . it is important to note the difference between the vco frequency (f vco ), and the data-rate frequency (df). f vco is always between 2 ghz to 3.2 ghz, while df is the divided down f vco that matches the input data-rate. 1.2.14 frequency refere nce acquisition (fra) when an external reference is applied to refclk , the fra mode is selected in either the hardwired or two-wire serial interface mode. frequency acquisition is enabled by the lolcir when lol = h ( alarm_lol = h or xlol = l). a secondary fll attempts to lock the vco to a frequency derived from the external reference. when the fre - quency is close to the desired frequency, lolcir sets lol = l and disables the secondary fll, thus, the main cdr pll is free to phase lock to the incoming data. although the main cdr pll can achi eve frequency lock, the vco frequency tuning range typically exceeds the cdr pll inherent acquisition range. this implies that the fll needs to get the vco within the cdr pll range. the loss of lock circuitry (lolcir) is used to determine when the secondary fll is active. the lolcir consists of window detectors that constantly compare a scaled vco fre - quency, to a frequency related to the external reference. when lol = h the loop is out of lock, the fll is activated until the frequency difference is within the narrow reference window (nrw). when lol = l, the fll is not engaged until the frequency exceeds the wide reference window (wrw). if a signal is not present, the fll circuit will drive the vco frequency to the nrw and turn off. without data present, the vco would then drift until the frequency dif - ference exceeds the wrw, and repeat this cycle. to prevent this, by default, the fll is activated with lol = h, or loa = h and the fll is not de-activated unless both lol = l and loa = l. table 1-9. valid input data ranges parameter df min df max units data-rate divider (drd = 1): cdr_ctrlb_ n [3:0] = 0000b 2.0 3.2 ghz data-rate divider (drd = 2): cdr_ctrlb_ n [3:0] = 0001b 1.0 1.6 ghz data-rate divider (drd = 4): cdr_ctrlb_ n [3:0] = 0010b 500 800 mhz data-rate divider (drd = 8): cdr_ctrlb_ n [3:0] = 0011b 250 400 mhz data-rate divider (drd = 12): cdr_ctrlb_ n [3:0] = 0100b 166.7 266.66 mhz data-rate divider (drd = 16): cdr_ctrlb_ n [3:0] = 0101b 125 200 mhz data-rate divider (drd = 24): cdr_ctrlb_ n [3:0] = 0110b 83.33 133.33 mhz data-rate divider (drd = 32): cdr_ctrlb_ n [3:0] = 0111b 62.5 100 mhz data-rate divider (drd = 48): cdr_ctrlb_ n [3:0] = 1000b 42 66.66 mhz
functional description 210xx-dsh-001-d mindspeed technologies? 14 mindspeed proprietary and confidential figure 1-7 shows a block diagram of the fra mode. the secondary fll for the fra mode compares a scaled ver - sion of the internal vco frequency (ifv) with a scaled vers ion of the reference clock frequency (ifr); ifr and ifv are limited to between 10 mhz and 25 mhz. the external reference clock frequency (f ref ) is applied to the refclk [p/n] terminals. this reference frequency is scaled to the ifr by the reference frequency divider (rfd) [ refclk_ctrl [3:1]], which allows for an external reference clock in the range of 10 mhz to 800 mhz. the rfd level is a globally set value that applies to all cdrs. ta bl e 1-10 gives the divider ratio, along with the minimum and maxi - mum f ref values. the vco frequency is scaled to the ifv by the vco comparison divider (vcd) [ cdr_ctrlc_ n [7:0]]. ta bl e 1-11 provides drd, rfd, and vcd values for common applications. for applications that only deal with sonet/sdh data-rates, a 19.44 mhz reference clock frequency must be used. for applications where a combination of sonet/sdh and other data-rates are used, a 25 mhz reference clock frequency must be used. if either of these reference clock frequencies is not available, pl ease contact mindspeed techno logies applications engi - neering for other options. figure 1-7. block diagram of fra mode table 1-10. reference clock frequency ranges rfd value minimum f ref (mhz) maximum f ref (mhz) rfd ( refclk_ctrl [3:1] = 000b): divide by 1 10 25 rfd ( refclk_ctrl [3:1] = 001b): divide by 2 20 50 rfd ( refclk_ctrl [3:1] = 010b): divide by 4 40 100 rfd ( refclk_ctrl [3:1] = 011b): divide by 8 80 200 rfd ( refclk_ctrl [3:1] = 100b): divide by 12 120 300 rfd ( refclk_ctrl [3:1] = 101b): divide by 16 160 400 rfd ( refclk_ctrl [3:1] = 110b): divide by 32 320 800 d in d out refclk lol loa dr f clk ifv ifr f vco f ref vco f vco,max > f vco > f vco,min cdr d in d out c in error fll error d 1 d 2 lolcir drd cdr_ctrlb_ n [3:0] vcd rfd cdr_ctrlc_ n [7:0] refclk_ctrl [3:1] c out c out
functional description 210xx-dsh-001-d mindspeed technologies? 15 mindspeed proprietary and confidential table 1-11. drd/rfd/vcd settings for different data-rates and reference frequencies application dr (mbps) fref (mhz) drd rfd vcd notes 10ge - xaui 3125 156.25 1 8 160 1 10ge-xaui 3125 25 1 2 250 10gfc - xaui 3187.5 159.375 1 8 160 1 10gfc-xaui 3187.5 25 1 2 255 2 sts-48+fec 2666.06 19.44 1 1 137 1, 2 sts-48 + fec 2666.06 25 1 2 213 2 sts-48 2488.32 155.52 1 8 128 1 sts-48 2488.32 19.44 1 1 128 1 sts-48 2488.32 25 1 2 199 2 2gfc 2125 106.25 1 8 160 1 2gfc 2125 25 1 2 170 ge 1250 125 2 8 160 1 ge 1250 25 2 2 200 fc 1062.5 106.25 2 8 160 1 fc 1062.5 25 2 2 170 2 sts-12 622.08 19.44 4 1 128 1 sts-12 622.08 25 4 2 199 2 fc 531 25 4 2 170 2 fc 266 25 12 2 255 2 escon 200 10 12 1 240 1 escon 200 25 12 2 192 sts-3 155.52 19.44 16 1 128 1 sts-3 155.52 25 16 2 199 2 fc 133 25 24 2 255 2 fe 125 12.5 16 1 160 1 fe 125 25 24 2 240 sts-1 51.84 25 48 2 199 2 sts-1 51.84 19.44 48 1 128 1, 2 ds3 44.736 25 48 2 172 2 notes: 1. bold text denotes standard hardwired rates. 2. set lol_ctrl _n[0] = 1b, all other bits at default values.
functional description 210xx-dsh-001-d mindspeed technologies? 16 mindspeed proprietary and confidential the fll drives the ifv to ifr, and it is the primary function of the lolcir to determine when to turn off the fll, so the cdr can achieve phase lock. the lol cir uses the frequency difference be tween ifv and ifr to switch lol, which turns on and off the secondary fll. the thresholds where lol makes a transition are defined as windows. these windows are fixed in the hardwired mode, and programmable in the two-wire interface mode. to prevent lol from toggling at the thresholds, two windows are used for hysteresis. when lol = l and the frequency differ - ence exceeds the larger window (wrw), lol l-to-h occurs to signal an out of lock case. when lol = h (and loa = l), the frequency difference is brought within the narrow reference window (nrw), after which lol makes a h- to-l transition signaling in-lock. if loa = h when lol = l, the fll remains on to keep the vco locked to the refer - ence, until a signal is present. n acq is defined with lol_ctrl _n [7:5], n narrow is defined with lol_ctrl _n [4:1], and n wide is defined with lol_ctrl _n [0]. the lolcir averages a large number of transitions before making an lol decision. this averaging time is referr ed to as the lol decision time or dt lol . ta bl e 1-12 shows various window sizes for different applications, including the default value in both the hardwired and two-wire serial interface modes. 1.2.15 ambient temperature range limitations ta bl e 1-13 summarizes the supported ambient temperature range as a function of data-rate, and indicates when it is required to center the vco. f vco is the vco frequency, which always lies in the range 2.0 - 3.2 ghz. dr is the data-rate of the input signal, and drd is the data-rate divider (1, 2, 4, 8, 12, 16, 24, 32, 48) set with cdr_ctrlb _n[3:0]. t a is the ambient tem - perature supported, which decreases for f vco > 2.666 ghz. as an example, if the data-rate is 800 mbps drd should be set to 4; to lock to this signal the vco needs to operate at 3.2 ghz. under these conditions the ambient temperature range supported is 0c - 70c, and it is necessary to center the vco in each of the four lanes. the vco tuning range is roughly the same bandwidth as the variation in vco center frequency between the extremes of the operating temperature range. this issue can be resolved by centering the vco frequency during the in-circuit testing (ict) phase prior to shipment of the customer systems. table 1-12. lol window size and decision time examples condition n acq n narrow n wide narrow window (ppm) wide window (ppm) decision time ( s) hardwired mode default 101b 0100b 0b 1955 2930 420 two-wire serial interface mode default 101b 0100b 0b 1955 2930 420 ifv = ifr 111b 0010b 1b 245 975 1685 fast lock 010b 0001b 0b 5860 7800 56 notes: 1. decision time is calculated with ifr = 19.44 mhz; will scale proportionally with ifr range from 10 to 25 mhz. 2. above are examples showing ability to tailor windows for data-rates, reference frequencies, and acquisition times. table 1-13. supported ambient temperature range by data-rate f vco (ghz) dr (gbps) t a ( c) vco centering requirement 2.0 - 2.666 2.0/drd - 2.666/drd -40 - 85 n 2.7 - 2.97 2.7/drd - 2.97/drd 0 - 70 n 2.7 - 2.97 2.7/drd - 2.97/drd -40 - 85 y 3.0 - 3.2 3.0/drd - 3.2/drd 0 - 70 y
functional description 210xx-dsh-001-d mindspeed technologies? 17 mindspeed proprietary and confidential 1. the cdr must be powered up and configured at 25c - 40c ambient temperature during ict. 2. power up the device and configure the registers via th e two-wire interface with the appropriate settings for the application of interest. 3. read and store the vco trim code from register mbh[4:0]. 4. every time the device is powered up, this trim code must be forced by setting m0h[0] = 0b then writing the code to mah[4:0]. this can be done during the same write cycle as when the other registers are configured. it should be noted that it is not possible to center the vco in the hardwired mode, it is necessary to program the cdr using the two-wire interface. 1.2.16 loss of activity by default, the loa detector is enabled and can be disabled by setting cdr_ctrla _n [1] = 0b, where n is the chan - nel number. loss of activity measures the transition dens ity of data to determine if the data is valid. with sonet data, the transition density is typically 50%, averaged over long periods. during small time intervals, data transition density variations are due to data content, packet headers, stress patterns, etc. in some applications, when data is not present, noise produces rail-to-rail transitions that cause problems with level based detectors. these applica - tions include cascaded cdrs, high-gain cr osspoints, as well as modules with op tical amplifiers. the data transition density based loa detector can separate data from random noise, determine false lock at the wrong integer and non-integer data-rate, signal stuck high/low conditions, and determine false lock to re-timed noise. unlike level based detectors, it cannot determine false lock onto low amplitude data, which is a condition that does not typically occur with backplane applications, and can be handled by the limiting amplifier or pre-amplifier in modules. the loa window is fixed at 12.5% from 50%; or alternatively if data with 50% transition density is present, the data- rate frequency can vary by 12.5% before an loa l-to-h transition occurs. if the data transition density of valid data falls outside the 37.5 - 62.5% window, the loa detector must be disabled. 1.2.17 built-in self test (bist) overview the m21012 contains a bist test pattern generator as well as a test pattern receiver. both the bist transmitter (bist tx), and bist receiver (bist rx) are designed to operate with fixed patterns. for sonet operation, the prbs 2 7 -1, 2 15 -1, 2 23 -1, and 2 31 -1 test patterns are provided. for 8b/10b testing, the fibre channel crpat and cjtpat standard patterns are supported. in addition, an 8b /10b countdown pattern is also provided; this is the 8b/ 10b representation of a binary count from 255 to 0, while maintaining 8b/10b running disparity requirements. user programmable 16 bit (sonet) and 20 bit (8b/10b) patterns are also provided; they are typically used to generate short patterns for debug, such as 1100b, as well as 8b/10b idle or control characters. the bist is designed to reduce system development time, as well as product test costs, and can be used by both the equipment provider as well as the equipment end user. when enabled, the bist rx allows one input from the cdr to enter the bist receiver. the desired channel to monitor is selected through a control register. the bist rx uses the recovered clock and data from the selected cdr to drive the pattern checker. every time a bit error is received, the error register is incremented. the maxi - mum number of errors is ffh, and all su bsequent errors will not be counted. at any time , the error register can be cleared. by keeping track of the time between a clear and a read, a rough ber number can be obtained. when enabled, the bist tx can broadcast the output test pattern to channels 0 and 1 (the bist tx and rx can be used at the same time). the bist tx contains an internal clock multiplier (pll), that can take its input from either the external reference frequency, or from the same cdr that is driving the bist rx (only in full-rate mode, drd = 1).
functional description 210xx-dsh-001-d mindspeed technologies? 18 mindspeed proprietary and confidential 1.2.18 bist test patterns the test pattern is selected with bisttx_ctrl [5:2] for the transmitter, and bistrx_ctrl [5:2] for the receiver. the prbs patterns generated by the unit are itu-t 0.151 compliant, and summarized in ta b l e 1-14 . for 8b/10b data, three patterns are available. the cjtpat and crpat comply with the fibre channel t11.2/ project 1230/rev10 specifications. two user programmable patterns that are 16 bits long ( bisttx_ctrl [5:2] = bistrx_ctrl [5:2] = 0111b) and 20 bits long ( bisttx_ctrl [5:2] = bistrx_ctrl [5:2] = 1000b) are determined with bist_pattern0 , bist_pattern1, bist_pattern2 . note that the contents of these registers are used by both the bist tx and the bist rx, if they are setup in this mode. 1.2.19 bist receiver (bist rx) operation the bist rx is powered up and enabled by setting bistrx_ctrl [1] = 1b (off by default), resetting the bist rx block with bistrx_ctrl [0] = 1b (default), and selecting a pattern with bistrx_ctrl [5:2]. the signal to the bist rx is routed from the input of the device, and the bist rx can only check one channel at a time. the desired channel to monitor is selected with bistrx_chsel [2:0]. the bist rx uses the recovered clock from the cdr to drive the bist state- machine, thus the cdr must be enabled and locked to data for proper operation. when the data is valid, bistrx_ctrl [6] = 1b is used to clear the error register, and all subsequent errors can be read back through bistrx_error . the bist rx automatically synchronizes the input data with the pattern. 1.2.20 bist transmitter (bist tx) operation the bist tx is powered up and enabled by setting bisttx_ctrl [1] = 1b (off by default), resetting the bist tx block with bisttx_ctrl [0] = 1b (default), and selecting a pattern with bisttx_ctrl [5:2]. the bist tx can multicast the test pattern to channels 0 and 1 selected with bisttx_chsel [1:0]. the high-speed clock of the bist tx is generated from its own frequency multiplier pll, that uses a selectable frequency reference determined by bisttx_ctrl [6]. with bisttx_ctrl [6] = 0b (default), the external reference clock is used and typically gives the lowest jitter output. with bisttx_ctrl [6] = 1b the reference clock is derived from the same cdr used to drive the bist rx (this feature only works with drd = 1 for that cdr). in this mode, the bist tx output is synchron ous with the cdr used in the bist rx, however, it contains the low-frequency jitter from the input data. in either case, the bist tx pll needs to table 1-14. bist prbs patterns bisttx_ctrl [5:2] / bistrx_ctrl [5:2] pattern polynomial 0000b prbs 2 7 -1 2 7 +2 6 +1 0001b prbs 2 15 -1 2 15 +2 14 +1 0010b prbs 2 23 -1 2 23 +2 18 +1 0011b prbs 2 31 -1 2 31 +2 28 +1 table 1-15. bist 8b/10b patterns bisttx_ctrl [5:2] / bistrx_ctrl [5:2] pattern 0100b cjtpat 0101b crpat 0110b countdown
functional description 210xx-dsh-001-d mindspeed technologies? 19 mindspeed proprietary and confidential be configured for the proper data-rate. when the pll is properly configured and locked to the reference, the lol flag should be low ( bisttx_alarm [7]). a bit error can be intentionally inserted into the bist tx output, by providing a 0b, 1b, 0b sequence to bisttx_ctrl [7] . the bist tx pll setup is similar to the cdr fra mode, thus, the description of similar registers for the cdr also applies and will not be repeated he re. the desired output data-rate is set with the drd register ( bisttx_pll_ctrlb [3:0]) and with the vcd register ( bisttx_pll_ctrlc [7:0]). the input reference frequency ifr is the same as for the main cdrs, since the same external reference and referenc e dividers are used. in the internal cdr case, ifr is f vco,rxcdr /128, where f vco,rxcdr is the vco frequency of the cdr selected by bistrx_chsel [2:0]. unlike the cdr, the tx pll always makes ifr equal to ifv, and bisttx_alarm [7] is used to determine if the tx pll is in lock. like the cdrs, if the output data-rate of th e bist tx needs to be changed, the bist tx requires a soft reset. 1.2.21 junction temp erature monitor an internal junction temperature monitor with a range of ?40c to 130c is integrated into the m21012. on the low end, the temperature monitor (tmon) is set to measure ?40c to 10c in six 10c steps, and on the high end, 80c to 130c in six 10c steps. the typical temperature resolution is 3c. the temperature monitor is enabled with te m p _ m o n [1] = 1b. when enabled, the temperature measurement cycle is achieved by providing a rising edge for te m p _ m o n [0]. afterwards, the correct temperature can be read from temp_value [3:0] . ta b l e 1-16 shows the map - ping of the temperature to temp_value [3:0] . enabling and strobing the temperature in the sa me write cycle will not yield reliable results. 1.2.22 ic identificati on / revision code the ic identification can be read back from chipcode, and the revision of the device can be read back from rev - code . the assigned ic identification for the m21012 is 12h, for the m21011 is 11h, for the M21001 is 10h, and the revision code is 20h. table 1-16. junction temperature monitor junction temperature temp_value [3:0] condition t j 130c 1100b high-alarm 130c > t j 120c 1011b high-alarm 120c > t j 110c 1010b high-warning 110c > t j 100c 1001b normal 100c > t j 90c 1000b normal 90c > t j 80c 0111b normal 80c > t j 10c 0110b normal 10c > t j 0c 0101b normal 0c > t j -10c 0100b normal -10c > t j -20c 0011b normal -20c > t j -30c 0010b low-warning -30c > t j -40c 0001b low-alarm -40c > t j 0000b low-alarm
functional description 210xx-dsh-001-d mindspeed technologies? 20 mindspeed proprietary and confidential 1.3 pin definitions table 1-17. power pins pin name function type vss ic ground power avdd_i/o analog i/o positive supply power avdd_core analog core positive supply power dvdd_i/o digital i/o positive supply power dvdd_core digital core positive supply power notes: 1. if internal regulator is enabled, connect all of the avdd_core and/or dvdd_core pins together to a common floating plane and bypass to vss . 2. if internal regulator is not enabled, it is recommended that all avdd_core pins be tied to a plane at 1.2v, that is bypassed to ground. dvdd_core can be tied to this plane or separately decoupled. 3. ic ground ( vss ) is established by contact with exposed pad on underside of package; there are no vss pins.
functional description 210xx-dsh-001-d mindspeed technologies? 21 mindspeed proprietary and confidential table 1-18. high-speed signal pins pin name function termination type din0p serial positive data input for channel 0 50 ? pull up to vddt0/1 i - universal din0n serial negative data input for channel 0 50 ? pull up to vddt0/1 i - universal din1p serial positive data input for channel 1 50 ? pull up to vddt0/1 i - universal din1n serial negative data input for channel 1 50 ? pull up to vddt0/1 i - universal din2p serial positive data input for channel 2 50 ? pull up to vddt2/3 i - universal din2n serial negative data input for channel 2 50 ? pull up to vddt2/3 i - universal din3p serial positive data input for channel 3 50 ? pull up to vddt2/3 i - universal din3n serial negative data input for channel 3 50 ? pull up to vddt2/3 i - universal vddt0/1 termination pin for din [1:0] terminate to avdd_i/o i - termination vddt2/3 termination pin for din [3:2] terminate to avdd_i/o i - termination dout0p serial positive data output for channel 0 50 ? pull up to avdd_i/o o - cml/lvds dout0n serial negative data output for channel 0 50 ? pull up to avdd_i/o o - cml/lvds dout1p serial positive data output for channel 1 50 ? pull up to avdd_i/o o - cml/lvds dout1n serial negative data output for channel 1 50 ? pull up to avdd_i/o o - cml/lvds dout2p serial positive data output for channel 2 50 ? pull up to avdd_i/o o - cml/lvds dout2n serial negative data output for channel 2 50 ? pull up to avdd_i/o o - cml/lvds dout3p serial positive data output for channel 3 50 ? pull up to avdd_i/o o - cml/lvds dout3n serial negative data output for channel 3 50 ? pull up to avdd_i/o o - cml/lvds cout0p serial positive clock output for channel 0 50 ? pull up to avdd_i/o o - cml/lvds cout0n serial negative clock output for channel 0 50 ? pull up to avdd_i/o o - cml/lvds cout1p serial positive clock output for channel 1 50 ? pull up to avdd_i/o o - cml/lvds cout1n serial negative clock output for channel 1 50 ? pull up to avdd_i/o o - cml/lvds cout2p serial positive clock output for channel 2 50 ? pull up to avdd_i/o o - cml/lvds cout2n serial negative clock output for channel 2 50 ? pull up to avdd_i/o o - cml/lvds cout3p serial positive clock output for channel 3 50 ? pull up to avdd_i/o o - cml/lvds cout3n serial negative clock output for channel 3 50 ? pull up to avdd_i/o o - cml/lvds refclkp reference clock positive input internal pull down i - ac coupled refclkn reference clock negative input internal pull down i - ac coupled
functional description 210xx-dsh-001-d mindspeed technologies? 22 mindspeed proprietary and confidential table 1-19. control, interface, and alarm pins pin name function default type mf0 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf1 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf2 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf3 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf4 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf5 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf6 multifunction pin for hardwired mode, and serial interface internal pull up i - cmos mf7 multifunction pin for hardwired mode internal pull up i - cmos mf8 multifunction pin for hardwired mode, and jtag internal pull up i - cmos mf9 multifunction pin for hardwired mode, and jtag internal pull up i - cmos mf10 multifunction pin for hardwired mode, serial interface, and jtag internal pull up i - cmos mf11 multifunction pin for hardwired mode, serial interface, and jtag internal pull up i - cmos ctrl_mode0 hardwired or two-wire serial interface mode control pin internal pull up i - cmos ctrl_mode1 hardwired or two-wire serial interface mode control pin internal pull up i - cmos out_mode0 output data interface control pin internal pull down i - cmos out_mode1 output data interface control pin internal pull down i - cmos xrst reset pin (l = reset) internal pull up i - cmos xjtag_en jtag testing control pin (l = enable) internal pull up i - cmos xregu_en internal voltage regulator control pin (l = enable) internal pull up i - cmos xloa0 loss of activity alarm pin for channel 0 (l = loa) no internal pull up/down o - open drain xloa1 loss of activity alarm pin for channel 1 (l = loa) no internal pull up/down o - open drain xloa2 loss of activity alarm pin for channel 2 (l = loa) no internal pull up/down o - open drain xloa3 loss of activity alarm pin for channel 3 (l = loa) no internal pull up/down o - open drain xlol0 loss of lock alarm pin for cdr at channel 0 (l = lol) no internal pull up/down o - open drain xlol1 loss of lock alarm pin for cdr at channel 1 (l = lol) no internal pull up/down o - open drain xlol2 loss of lock alarm pin for cdr at channel 2 (l = lol) no internal pull up/down o - open drain xlol3 loss of lock alarm pin for cdr at channel 3 (l = lol) no internal pull up/down o - open drain
functional description 210xx-dsh-001-d mindspeed technologies? 23 mindspeed proprietary and confidential figure 1-8. m21012 pinout diagram (top view) dout0p dout0n avdd_core mf10 mf4 mf5 mf6 xlol0 xjtag_en ctrl_mode0 ctrl_mode1 mf3 din2n xregu _en din1n avdd_core avdd_core din2p avdd_i/o din1p din0n vddt0/1 1 2 3 4 5 6 7 8 9 10 11 12 19 20 21 22 23 24 25 26 27 28 29 30 43 44 45 46 47 48 49 50 51 52 53 54 72 71 70 69 68 67 66 65 64 63 62 61 cout1p cout1n avdd_core dout1p dout1n avdd_i/o avdd_i/o dout2p dout2n avdd_core cout2p cout2n avdd_core dout3p dout3n 60 59 58 57 56 55 39 40 41 42 37 38 din0p din3p dvdd_core vddt2/3 avdd_core din3n xlol1 31 32 33 34 35 36 mf1 mf2 mf0 cout0n cout0p avdd_i/o 13 14 15 16 17 18 avdd_i/o cout3p cout3n mf9 mf8 refclkp refclkn xloa3 xloa2 xloa1 xloa0 out_mode1 out_mode0 mf7 xrst xlol2 xlol3 avdd_core dvdd_core dvdd_core dvdd_i/o mf11
210xx-dsh-001-d mindspeed technologies? 24 mindspeed proprietary and confidential 2.0 product specifications 2.1 absolute maximum ratings these are the absolute maximum ratings beyond which the device can be expected to fail or be damaged. reliable operation at these extremes for any length of time is not warranted. table 2-1. absolute maximum ratings symbol parameter notes minimum typical maximum units dvdd_i/o digital i/o power 0 1.8/2.5/3.3 3.6 v avdd_i/o analog i/o power 0 1.8/2.5/3.3 3.6 v avdd_core analog core power 2 0 1.2 1.5 v dvdd_core digital core power 2 0 1.2 1.5 v ? high-speed signal pins 3 vss - 0.5 ? avdd_i/o + 0.5 v ? control, interface, and alarm pins 4 vss - 0.5 ? dvdd_i/o + 0.5 v t st storage temperature ?65 ? +150 c esd human body model (low-speed) 2000 ? ? v esd human body model (high-speed) 1000 ? ? v esd charged device model 100 ? ? v notes: 1. no damage under typical conditions. 2. apply voltage to core pins if intern al regulator is disa bled. if enabled, pins should be floating with by-pass to vss . 3. high-speed signal pins are shown in table 1-18 . 4. control, interface, and alarm pins are shown in table 1-19 .
product specifications 210xx-dsh-001-d mindspeed technologies? 25 mindspeed proprietary and confidential 2.2 recommended operating conditions 2.3 power dissipation table 2-2. recommended operating conditions symbol parameter notes minimum typical maximum units dvdd_i/o digital i/o power 2 ? 1.8/2.5/3.3 ? v avdd_i/o analog i/o power 2 ? 1.8/2.5/3.3 ? v avdd_core analog core power 1, 2 ? 1.2 ? v dvdd_core digital core power 1, 2 ? 1.2 ? v t a ambient temperature 4 - 40 ? 85 c ja junction to ambient thermal resistance 3 ? 24 ? c/w notes: 1. needed only if avdd_core or dvdd_core are provided from external source (internal regulator disabled xregu_en = h). 2. typical value +/- 5% is acceptable. 3. with forced convection of 1 m/s and 2.5 m/s, ja is decreased to 18c/w and 16c/w respectively. 4. this temperature range is supported when the vco operates betw een 2.0 - 2.666 ghz, or for data rates between 2.0/drd - 2.666/ drd gbps, where drd = data-rate divider. for higher data-rates, t a is supported in the range 0c - 70c and the device should be powered up and config- ured at room temperature. for details, see section 1.2.15 . table 2-3. dc power electrical specifications (1 of 2) symbol parameter notes minimum typical maximum units idd case 1: current consumption for output swing = 600 mv cml, internal regulator = on, clock outputs = off 1 ? 310 365 ma pdiss power dissipation at 1.8v ? ? 560 660 mw pdiss power dissipation at 3.3v 2 ? 1.02 1.2 w idd case 2: current consumption for output swing = 600 mv cml, internal regulator = on, clock outputs = on 1 ? 370 435 ma pdiss power dissipation at 1.8v ? ? 670 780 mw pdiss power dissipation at 3.3v 2 ? 1.22 1.44 w idd case 3: current consumption for output swing = 1v cml, internal regulator = on, clock outputs = off 1 ? 340 400 ma pdiss power dissipation at 1.8v ? ? 610 720 mw pdiss power dissipation at 3.3v 2 ? 1.12 1.32 w idd case 4: current consumption for output swing = 1v cml, internal regulator = on, clock outputs = on 1 ? 420 490 ma pdiss power dissipation at 1.8v ? ? 760 880 mw pdiss power dissipation at 3.3v 2 ? 1.39 1.62 w
product specifications 210xx-dsh-001-d mindspeed technologies? 26 mindspeed proprietary and confidential case 5: output swing = 600 mv cml, internal regulator = off, clock outputs = off 1 idd_core core current consumption ? ? 260 300 ma idd_io input/output buffers current consumption ? ? 50 70 ma pdiss power dissipation at 1.2v core, 1.8v i/o ? ? 400 490 mw pdiss power dissipation at 1.2v core, 3.3v i/o ? ? 480 590 mw case 6: output swing = 600 mv cml, internal regulator = off, clock outputs = on 1 idd_core core current consumption ? ? 285 330 ma idd_io input/output buffers current consumption ? ? 100 125 ma pdiss power dissipation at 1.2v core, 1.8v i/o ? ? 520 620 mw pdiss power dissipation at 1.2v core, 3.3v i/o ? ? 670 810 mw idd case 7: current consumption for output swing = 450 mv lvds, internal regulator = on, clock outputs = off 1 ? 320 380 ma pdiss power dissipation at 1.8v ? ? 580 680 mw pdiss power dissipation at 3.3v 2 ? 1.06 1.25 w idd case 8: current consumptio n for output swing = 1.6v pcml+, internal regulator = on, clock outputs = off 1 ? 410 470 ma pdiss power dissipation at 1.8v ? ? 740 850 mw pdiss power dissipation at 3.3v 2 ? 1.35 1.55 w notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. thermal design such as thermal pad vias on pcb must be considered for this case. table 2-3. dc power electrical specifications (2 of 2) symbol parameter notes minimum typical maximum units
product specifications 210xx-dsh-001-d mindspeed technologies? 27 mindspeed proprietary and confidential 2.4 input/output specifications table 2-4. two-wire serial interface cmos i/o electrical specifications symbol parameter notes minimum typical maximum units v oh output logic high i oh = ?3 ma 2 0.8 x dvdd_i/o dvdd_i/o ? v v ol output logic low i ol = 24 ma 2 ? 0.0 0.2 x dvdd_i/o v i ol output current (logic low) ? 10 ? ? ma v ih input logic high ? 0.75 x dvdd_i/o ? 3.6 v v il input logic low ? 0 ? 0.25 x dvdd_i/o v i ih input current (logic high) ? ?100 ? 100 a i il input current (logic low) ? ?100 ? 100 a t r output rise time (20-80%) ? ? ? 5 ns t f output fall time (20-80%) ? ? ? 5 ns c2wire input capacitance of mf10 & mf11 in two-wire serial mode 3 ? ? 10 pf notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. dvdd_i/o can be chosen independently from avdd_i/o . 3. two-wire serial output mode can drive 500 pf.
product specifications 210xx-dsh-001-d mindspeed technologies? 28 mindspeed proprietary and confidential table 2-5. universal high-speed (uhs) input electrical specifications symbol parameter notes minimum typical maximum units dr in input signal data-rate 3 42 ? 3200 mbps v id input differential voltage (p-p) 4,5 100 ? 2000 mv v icm input common-mode voltage ? vss ? avdd_i/o mv v ih maximum input high voltage ? ? ? avdd_i/o + 400 mv v il minimum input low voltage ? vss - 400 ? ? mv ? maximum voltage difference between common- mode voltage and vddt ? ? ? 600 mv r in input termination to vddt 7 45 50 65 ? s 11 input return loss (40 mhz to 2.5 ghz) ? ? ?15.0 ? db s 11 input return loss (2.5 ghz to 5 ghz) ? ? ?5.0 ? db ? maximum dc input current 6 ? ? 25 ma notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. designed for seamless interface to pcml. 3. designed for sonet and 8b/10b data. 4. example 1200 mv pp differential = 600 mv pp for each single-ended terminal. 5. minimum input level defined as error free operation at 10 -12 ber. 6. computed as the current through 50 ? from the voltage difference between the input voltage common mode and vddt. 7. see figure 2-1 for input termination circuit. figure 2-1. data input internal circuitry dinp dinn data input buffer vdd_core r >> 50 ? r >> 50 ? 50 ? 50 ? vddt 5 pf 5 pf
product specifications 210xx-dsh-001-d mindspeed technologies? 29 mindspeed proprietary and confidential table 2-6. pcml (positive current mode logic) output electrical specifications symbol parameter notes minimum typical maximum units dr out output signal data-rate ? 42 ? 3200 mbps t r /t f rise/fall time (20-80 %) for all levels ? ? 75 130 ps v oh low swing: output logic high (single-ended) ? avdd_i/o ? 25 ? avdd_i/o mv v ol low swing: output logic low (single-ended) ? avdd_i/o ? 370 ? avdd_i/o ? 260 mv v od low swing: differential swing 2 500 600 700 mv v oh medium swing: output logic high (single-ended) ? avdd_i/o ? 30 ? avdd_i/o mv v ol medium swing: output logic low (single-ended) ? avdd_i/o ? 600 ? avdd_i/o ? 440 mv v od medium swing: differential swing 2 800 1000 1200 mv cv od clock output differential swing: medium setting 2 640 ? ? mv v oh high swing: output logic high (single-ended) ? avdd_i/o ? 30 ? avdd_i/o mv v ol high swing: output logic low (single-ended) ? avdd_i/o ? 770 ? avdd_i/o ? 550 mv v od high swing: diff erential swing 2 1000 1300 1500 mv v oh pcml+ swing: output logic high (single-ended) ? avdd_i/o ? 35 ? avdd_i/o mv v ol pcml+ swing: output logic low (single-ended) ? avdd_i/o ? 1000 ? avdd_i/o ? 700 mv v od pcml+ swing: differential swing 2 1300 1600 2000 mv r out output termination to avdd_i/o ? 45 50 65 ? s 22 output return loss (40 mhz to 2.5 ghz) ? ? ?15.0 ? db s 22 output return loss (2.5 ghz to 5 ghz) ? ? ?5.0 ? db notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. example 1200 mv p-p differential = 600 mv p-p for each single-ended terminal. 3. all output swings defined with pre-emphasis off. 4. clock output swing is typically 20% less than data output swing, and clock output rise/fall time is typically 30% less than d ata output rise/fall time.
product specifications 210xx-dsh-001-d mindspeed technologies? 30 mindspeed proprietary and confidential table 2-7. lvds (low voltage differential signal) output electrical specifications symbol parameter notes minimum typical maximum units dr out output signal data-rate ? 42 ? 800 mbps v ocm output average common mode range 2 1125 ? 1275 mv t r /t f gpl: rise/fall time (20-80%) ? ? 75 130 ps v od gpl: differential output (p-p) 3 500 650 800 mv v od rrl: differential output (p-p) ? 300 450 550 mv r out output termination (differential) ? 90 100 130 ? s 22 output return loss (40 mhz to 2.5 ghz) ? ? ? 15.0 ? db s 22 output return loss (2.5 ghz to 5 ghz) ? ? ? 5.0 ? db notes: 1. specified at recommended operating conditions - see table 2-2 . 2. computed as average (average positive output and average negative output). 3. conforms to ieee std 1596.3-1996 for gpl. all values specified for 50 ? single-ended back-match, 100 ? differential load. 4. all output swings defined with pre-emphasis off. 5. clock output swing is typically 10% less than data output swing, and clock output rise/fall time is typically 20% less than d ata output rise/fall time. table 2-8. input equalization performance specifications symbol parameter notes minimum typical maximum units dr in input signal data-rate ? 42 ? 3200 mbps ? maximum error-free di stance at 3.1875 gbps 2, 3, 6 ? ? 60 in ? maximum error-free di stance at 2.125 gbps 2, 3, 6 ? ? 72 in notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. performance measured on standard fr4 backplane such as standards provided by tyco for 10ge xaui. 3. measured with pcml driver without output pr e-emphasis at a minimum launch voltage of 1 vpp output sw ing at beginning of line. 4. combined input equalization + output pre-emphasis performance will be better than individual performance, but less than the s um of the two lengths. 5. input equalization has greatest effect for data-ra tes higher than 1 gbps. 6. default setting optimized for driving 10 - 46 in of pcb trace length. equalizer can be configured for longer reach using two- wire interface. 7. test setup: pattern generator test backplane dut error detector.
product specifications 210xx-dsh-001-d mindspeed technologies? 31 mindspeed proprietary and confidential table 2-9. output pre-emphasis performance specifications symbol parameter notes minimum typical maximum units dr out output signal data-rate ? 42 ? 3200 mbps ? maximum error-free distance at 3.1875 gbps 2 ? ? 40 in ? maximum error-free distance at 2.125 gbps 2 ? ? 60 in notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. performance measured on standard fr4 backplane such as standards provided by tyco for 10ge xaui. 3. measured with pcml receiver without input equalization, usi ng pcml output driver at 1300 mvpp output swing at beginning of li ne. 4. combined input equalization + output pre-emphasis performance will be better than individual performance, but less than the s um of the two lengths. 5. output pre-emphasis has greatest eff ect for data-rates higher than 1 gbps. 6. test setup: pattern generator dut test backplane error detector. table 2-10. reference clock input symbol parameter notes minimum typical maximum units f ref input frequency ( refclk_ctrl [3:1] = 000b) 2,3 10 19.44 25 mhz f ref input frequency ( refclk_ctrl [3:1] = 001b) 2,3 20 38.88 50 mhz f ref input frequency ( refclk_ctrl [3:1] = 010b) 2,3 40 77.76 100 mhz f ref input frequency ( refclk_ctrl [3:1] = 011b) 2,3 80 155.52 200 mhz f ref input frequency ( refclk_ctrl [3:1] = 100b) 2 120 250 300 mhz f ref input frequency ( refclk_ctrl [3:1] = 101b) 2,3 160 311.04 400 mhz f ref input frequency ( refclk_ctrl [3:1] = 110b) 2,3 320 622.08 800 mhz v id input differential voltage (p-p) 4,5 100 ? 1600 mv v icm input common-mode voltage 2,5 250 ? avdd_i/o mv ? input duty cycle ? 40 50 60 % ? frequency stability 2 ? ? 100 ppm r in differential termination 5 ? 100 ? ? ? internal pull-down to vss ? ? 100 ? k ? ? maximum dc input current ? ? ? 15 ma notes: 1. specified at recommended operation conditions ? see table 2-2 . 2. used for frequency reference cdr acquisition. 3. typical values are exact integer ratios for sonet applications. 4. example 1200 mv pp differential = 600 mv pp for each single-ended terminal. 5. input can accept a cmos single-ended clock on differential p term inal when differential n terminal is decoupled to ground wit h a large enough capacitor. cmos input will then see an effective 100 ? load. 6. see figure 2-2 for input termination circuit.
product specifications 210xx-dsh-001-d mindspeed technologies? 32 mindspeed proprietary and confidential 2.5 cdr performance specifications figure 2-2. reference clock input internal circuitry table 2-11. cdr high-speed performance (1 of 3) symbol parameter notes minimum typical maximum units dr in input signal data-rate (nrz data) divider ratio = 1 ? 2 ? 3.2 gbps dr in input signal data-rate (nrz data) divider ratio = 2 ? 1 ? 1.6 gbps dr in input signal data-rate (nrz data) divider ratio = 4 ? 500 ? 800 mbps dr in input signal data-rate (nrz data) divider ratio = 8 ? 250 ? 400 mbps dr in input signal data-rate (nrz data) divider ratio = 12 ? 167 ? 267 mbps dr in input signal data-rate (nrz data) divider ratio = 16 ? 125 ? 200 mbps dr in input signal data-rate (nrz data) divider ratio = 24 ? 83 ? 133 mbps dr in input signal data-rate (nrz data) divider ratio = 32 ? 62.5 ? 100 mbps dr in input signal data-rate (nrz data) divider ratio = 48 ? 42 ? 67 mbps j tol jitter tolerance ( figure 2-4 ) 2 ? 0.625 ? ui j trf jitter transfer ( figure 2-5 ) 2, 16 ? ? ? ? j gen jitter generation (rms) at sts-n (n = 1, 3, 12, 48) 2, 12 ? 4.5 6.5 mui j gen jitter generation (pp) at sts-n (n = 1, 3, 12, 48) 2, 12 ? 30 55 mui 0.5 pf 0.5 pf refclkp refclkn clock input buffer vdd_core 150 k ? 150 k ? 100 ? 100 k ? 100 k ? vss vss
product specifications 210xx-dsh-001-d mindspeed technologies? 33 mindspeed proprietary and confidential f lbw default loop bandwidth: divider ratio = 1 3,4,5 ? ? 2 mhz f lbw default loop bandwidth: divider ratio = 2 3,4,5 ? ? 1 mhz f lbw default loop bandwidth: divider ratio = 4 3,4,5 ? ? 500 khz f lbw default loop bandwidth: divider ratio = 8 3,4,5 ? ? 250 khz f lbw default loop bandwidth: divider ratio = 12 3,4,5 ? ? 167 khz f lbw default loop bandwidth: divider ratio = 16 3,4,5 ? ? 125 khz f lbw default loop bandwidth: divider ratio = 24 3,4,5 ? ? 83 khz f lbw default loop bandwidth: divider ratio = 32 3,4,5 ? ? 62.5 khz f lbw default loop bandwidth: divider ratio = 48 3,4,5 ? ? 41.6 khz r j output data random jitter (pp) 13 ? ? 100 mui d j output data deterministic jitter (pp) 13 ? ? 110 mui t j output data total jitter (pp) 13 ? ? 210 mui j rms output data broadband jitter (rms) 14, 15 ? 13 40 mui j pp output data broadband jitter (pp) 14, 15 ? 75 230 mui t sk delay from falling edge of positive clock output to data transition ( figure 2-3 ) ? -50 ? 50 ps j rms output clock broadband jitter (rms) 14, 15 ? 13 40 mui j pp output clock broadband jitter (pp) 14, 15 ? 75 230 mui c dc output clock duty cycle ? 45 50 55 % d dc output data duty cycle ? 45 50 55 % t lat latency from input to output (utilizing cdr) ? ? 1.75 2 ns table 2-11. cdr high-speed performance (2 of 3) symbol parameter notes minimum typical maximum units
product specifications 210xx-dsh-001-d mindspeed technologies? 34 mindspeed proprietary and confidential ch sk channel to channel output data skew (utilizing cdr) ? ? 10 65 ps ? initialization time 6,7,10 2 ? ms t fra frequency acquisition time 6,8 0.4 ? ms t pll phase lock time with 100 ppm delta f 9,11 100 ns t pll phase lock time with 0 ppm delta f 9,11 50 ns notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. jitter tolerance, jitter transfer, and jitter generation specified with input equalization and output pre-emphasis disabled, utilizing prbs 2 23 -1, per gr-253 test methodologies. 3. nominal loop bandwidth for 2.48832 ghz/ drd. 4. bandwidth is proportional to frequency. 5. for sonet data-rates, default meets sonet specifications. 6. assume that reference is within +/-100 ppm of desired data-rate. 7. time after power up, reset, or data-rate change. 8. time from application of valid data to lock within +/-20% of lock phase. 9. defined as when phase settles to within 20% of lock phase. 10. after reset (master or so ft), initialization takes place, then frequency acquisition. 11. based on nominal sonet bandwidth (bandwidth can be increased for lower phase lock time). 12. jitter generation specified per gr-253, utilizing ba ndpass filter with passband 12 khz to 20 mhz for sts-48. 13. r j , d j , t j represent jitter measured to ber of 10 -12 per fc-pi-2 specifications. 14. broadband jitter defined as jitter measured on sam pling oscilloscope wit hout the use of filters. 15. maximum value specified incorporates asynchronous aggressors. 16. jitter transfer of cdr meets the sonet sts-48 mask if loop bandwidth is set to 80% of nominal by writing phadj_ctrl _n[5:4] = 00b. jitter trans - fer at sts-12 (sts-3) exceeds mask by 0.1 db in frequency range 10 - 25.1 khz (1.5 - 10 khz). figure 2-3. clock to data output skew timing table 2-11. cdr high-speed performance (3 of 3) symbol parameter notes minimum typical maximum units dout [p/n] coutp t sk
product specifications 210xx-dsh-001-d mindspeed technologies? 35 mindspeed proprietary and confidential figure 2-4. jitter tolerance specification mask figure 2-5. jitter transfer specification mask input jitter amplitude (uipp) slope = -20 db/decade 6k 15 10 / n 600 / n 100k 214k 1.5 j jitter frequency (hz) 0.15 mindspeed specification 1m / n gr-253 sonet specification / n / n / n tol slope = -20 db/decade 2m / n 0.1 jitter gain (db) jitter frequency (hz) mindspeed and gr-253 sone t specification
product specifications 210xx-dsh-001-d mindspeed technologies? 36 mindspeed proprietary and confidential table 2-12. cdr alarm performance symbol parameter notes minimum typical maximum units dt loa xloa decision time 5 ? 26 ? s ? xloa assertion transition density threshold ( xloa = h to l) 5, 6 ? 12.5 ? % ? xloa de-assertion transiti on density threshold ( xloa = l to h) 5, 6 ? 12.5 ? % dt lol xlol decision time (measurement time) 2 10 420 3275 s wrw xlol assertion frequency threshold ( xlol = h to l) 2,3 185 2930 250000 ppm nrw xlol de-assertion frequency threshold ( xlol = l to h) 2,3 120 1955 250000 ppm notes: 1. specified at recommended operating conditions ? see table 2-2 . 2. actual time is set with lol window. typical is the default value. minimum and maximum indicate dynamic range. 3. assume that reference is +/-100 ppm of operating frequency. 4. computed for 2.48832 gbps data-rate. will scale with data-rate. 5. fixed values. 6. specification shown represents deviation from 50% transition density.
product specifications 210xx-dsh-001-d mindspeed technologies? 37 mindspeed proprietary and confidential 2.6 package drawings and surface mount assembly details the m21012 is assembled in 72-pin 10 mm x 10 mm microleadframe (mlf) packages. this is a plastic encapsulated package with a copper leadframe. the mlf is a leadless package with lands on the bottom surface of the package. the exposed die paddle serves as the ic ground ( vss ), and the primary means of thermal dissipat ion. this die paddle should be soldered to the pcb. a cross-section of the mlf package can be found in figure 2-6 . figure 2-6. cross-section of mlf package mold compound gold wire die attach material exposed die paddle ground bond down bond cu leadframe solder plating ag platin g die
product specifications 210xx-dsh-001-d mindspeed technologies? 38 mindspeed proprietary and confidential figure 2-7 shows the package outline drawing for the 68-pin 10 mm x 10 mm mlf package ( note: see figure 2-8 for dimensions of 72- pin package). figure 2-7. 68-pin package drawing 0.80 dia. d1/2 d1 d/2 d e1/2 e/2 e1 e 2x a 2x 0.10 b c a n seating plane 56 2 3 1 0.08 c c 0.10 2x a 0.10 0.10 2x b 0 a1 10 c c c a3 a2 a b top view side view 0.10 b a m c seating plane n b e 1 l ref. (nd-1)xe (ne-1)xe ref. 4 2 3 4x p 4x p d2 d2/2 e2 e2/2 pin1 id 0.20 r. 0.45 0.25 min 0.25 min. see detail "a" for pin #1 id and tie bar mark option bottom view terminal tip c l e for odd terminal/side terminal tip e l c c c for even terminal/si de b 4 scale: none a1 11 section "c-c"
product specifications 210xx-dsh-001-d mindspeed technologies? 39 mindspeed proprietary and confidential t he relevant dimensions for the 72-pin version of the package can be found in figure 2-8 . figure 2-8. 72-pin package dimensions m nd e n b l d2 q e2 ne y s pitch variation d nom. 18 72 0.23 0.40 0.20 18 0.50 bsc see exposed pad variation:c see exposed pad variation:c 0.18 0.30 0.00 min. o l b 3 0.30 0.50 0.45 4 max. o n t 3 3 e 12 12 dimensions d p 0.24 r 0.13 d1 e1 0 e o l b a a1 a2 a3 - min. - 0.00 y m s 10.00 bsc 0.60 0.23 0.42 0.17 9.75 bsc 9.75 bsc 10.00 bsc 12? max. 0.20 ref. nom. 0.85 0.01 0.65 0.90 0.05 0.70 common e o t 11 n variations exposed pad symbols min min max nom d2 nom max e2 note 5.85 5.85 c 6.15 6.00 6.00 6.15 dimension b applies to plated terminal and is measured 1. die thickness allowable is 0.305mm maximum(.012 inches maximum) notes: 2. dimensioning & tolerances conform to asme y14.5m. - 1994. 4. 7. all dimensions are in millimeters. package by using indentation mark or other feature of package body. the pin #1 identifier must be existed on the top surface of the 5. exact shape and size of this feature is optional. 6. n is the number of terminals. nd is the number of terminals in x-direction & ne is the number of terminals in y-direction. 3. between 0.20 and 0.25mm from terminal tip. package warpage max 0.08mm. 9. applied only for terminals. 10. applied for exposed pad and terminals. 11. exclude embedding part of exposed pad from measuring. q and r applies only for straght tiebar shapes. 12. 8. the shape shown on four corners are not actual i/o. detail "a" - pin #1 id and tie bar mark option standard
product specifications 210xx-dsh-001-d mindspeed technologies? 40 mindspeed proprietary and confidential the m21012 evaluation module (evm) uses the pcb footprint shown in figure 2-9 . figure 2-9. pcb footprint for 72-pin 10 mm mlf package note : pads placed on a .374 mils square (9.5 mm). add as many vias to ground in .290 square pad as possible. add .025 round clearances on soldermask in an even pattern to help solder ground pad.
product specifications 210xx-dsh-001-d mindspeed technologies? 41 mindspeed proprietary and confidential the pad length dimensions should account for component tolerances, pcb tolerances, and placement tolerances. at a minimum, the pad should extend at least 0.1 mm on the outs ide and 0.05 mm on the inside, as shown in figure 2-10 . to efficiently dissipate heat from the m21012, a thermal pad with thermal vias should be used on the pcb. an example of a therm al pad with a 4x4 via array is shown in figure 2-11 . the thermal vias provide a heat conduction pa th to inner and/or bottom layers of the pcb. the larger the via array, the lower the thermal resistance ( ja ) . it is recommended to use thermal vias with 1.0 to 1.2 mm pitch with 0.3 to 0.33 mm via diameter. for further details please refer to the relevant application note from package vendor amkor (see list of references at the end of this document). much of the material in this section has been adopted from the amkor smt application note. 2.7 pcb high-speed design and layout guidelines a single power plane for the avdd_io and avdd_core power supplies with bulk capacitors (typically 10 f) distrib - uted throughout the board will mitigate most power-rail related volta ge transients. a bulk capacitor should also be placed where the power enters the board. it is recommended that decoupling capacitors only be routed directly to the power pin if they can be placed within 1/8 of an in ch of the pin. decoupling capacitors should be dispersed around the outside of the device on the top side and underneath the ic on the bottom side of the board. it is recom - mended that 0.1 f and 0.01 f decoupling capacitors be used. all three capacitor values are not required on each pin, but should be dispersed uniformly to filter different frequencies of noise. a continuous ground plane is the best way to minimize ground impedance. return currents and power supply tran - sients produce most ground noise during switching. reducing ground plane impedance minimizes this effect. there is a high frequency decoupling effect from the capacitive effect of power/ground planes and this can be used to help minimize the amount of high frequency decoupling capacitors. figure 2-10. pcb pad extensions figure 2-11. recommended via array for thermal pad .1 mm .05m m pcb pad
product specifications 210xx-dsh-001-d mindspeed technologies? 42 mindspeed proprietary and confidential high-speed pcml signals should be routed with 50 ? equal length traces for p and n signals within each differen - tial pair. buried strip line is recommended for internal laye rs while microstrip line is us ed for signals routed on sur - face layers. there should be no discontinuity in the ground planes during the path of the signal traces. impedance discontinuities occur when a signal passes th rough vias and travels between layers. it is recommended to minimize the number of vias and layers that the transm it/receive signals travel through in the design. the system pcb should be designed so that high-speed signals pass th rough a minimal number of vias and remain on a single internal high-speed routing layer. when vias need to be used, the via design should matc h the transmission line impedance by observing the follow - ing: avoid through-hole vias; they cause stubs by extending the full cross-section of the pcb despite the fact that the layer change requires only a small length via (as in the case of adjacent layers). use short blind vias. avoid layer changes in general as the characteristic impedance of the transmission line changes as a result. in general, some rules of thumb for pcb design for high data-rates are: pcb trace width for high-speed signals should closel y match the smt component width, so as to prevent stub effects from a sudden change in stripline width. a gradual increase in trace width is recommended as it meets the smt pad. the pcb ground/power planes should be removed from under the i/o pins so as to reduce parasitic capac - itance. high-speed traces should avoid s harp changes in direction. using large radii will minimize impedance changes. avoid bending traces by more than 45 degrees; otherwise, provide a circular bend so as to pre - vent the trace width from widening at the bend. avoid trace stubs by minimizing components (resistors , capacitors) on the board. for instance, a termina - tion resistor at the input of a receiver will inflict a stub effect at high frequency. termination resistors inte - grated on chip will eliminate the stub. components designed to dc co uple to one anothe r avoid the need for coupling capacitors and the inherent stubs created from them. for high-speed differential signals, the trace lengths of each side of the differential pair should be matched to each other as much as possible. the skew between the p and n signals in a differential pair should be tightly controlled in order for the differential receiver to detect a valid data transition. when matching trace-lengths within a differen - tial pair, care should be taken to avoid introducing la rge impedance discontinuities. the figures below show two methods of matching the trace-lengths for a differential pair. typically, the preferred solution for trace-length matching in differential pairs is to use a serpentine pattern for the shorter signal as shown in figure 2-12 . using a serpentine patter n for length matching will minimize the differential impedance discontinuity while making both trace-lengths equal. figure 2-12. trace-length matching using serpentine pattern
product specifications 210xx-dsh-001-d mindspeed technologies? 43 mindspeed proprietary and confidential the loop length matching method shown in figure 2-13 will match the trace lengths of a differential pair, but will create a large impedance discontinuity in the transmission line, which could result in higher jitter on the signal and/ or a greater sensitivity to noise for the differential pair. when using capacitors to ac-couple the input, care shoul d be taken to minimize the pattern-dependant jitter (pd j ) associated with the low-frequency cutoff of the coupling ne twork. when nrz data containing long strings of 1s or 0s is applied to a high-pass filter, a voltage droop occurs. this voltage droop causes pd j in much the same fashion as inter-symbol interference (isi) is generated from dispersion effects of long trace-lengths in backplane material. if needed, use 0.1 f capacitors to ac-couple the high-speed output signals, and the reference clock inputs. the high-speed data input signals can be dc-coupled. on the evaluation module (evm), we have tied dvdd_i/o and avdd_i/o together to minimize the number of power supply jacks. they are kept separate on-chip to give the flexib ility to the system designers to supply a different volt - age level for each. for instance, an fpga can be used to supply power to dvdd_i/o , while a lower voltage can be used to power avdd_i/o to minimize power dissipation. on the evm, we have also tied dvdd_core and avdd_core together to minimize the number of power supply jacks. they are kept separate on-chip to provide more isolation, however, if the system board plan e is properly decoupled, they can be tied together. no inductive filtering on the system boa rd is necessary between different powe r supplies of the ic. it is up to the system designer to determine if this needs to be considered for supplies that are coming from other parts of the system board (such as switching regulators or asics). an inductor should not be used at the vddt pins. these pins were made available to create a low ac impedance, such that the 50 ? on-chip termination impedances see a common ac ground. this assures both common-mode and differential termination. if common-mode termination is not important (such as in lvds applications), simply leave the vddt pins floating. note that a low ac impedance can also be created by tying the vddt pins to the avdd_i/o plane, thus saving on the number of external capacitors. this, however, implies a cml-like data interface (unless the data is ac-coupled). vddt is not really a supply plane on-chip, it is simply the point to which the 50 ? input impedances are tied. power planes should be decoupled to ground planes using thin dielectric layers, to increase capacitance (prefera - bly 2-4 mils). reference ground layers should be used on both sides of inner layer routing planes, with controlled impedance. the total board thickness sh ould meet the sta ndard drill holes to board thic kness ratio of 1:12 or 1:14. use 1/2 ounce copper clad on all layers, which is approxim ately 0.7 mils. avoid placing solder mask and silk-screen on top of transmission lines; solder mask will add 1 - 2 ? to the overall impedance of th e transmission line. dielectric core material should be used wherever possible, as it will maintain its thic kness and geometry during processing, better than pliable prepreg. the microwave ground should follow the transmission line from end to end, or from signal input to output. it is best to designate layers as dedicated microwave/circuit grou nd planes, and properly isolate them from other ground planes by providing adequate distance. all microwave ground planes should be tied together. uncoupled microstrip transmission lines should be placed at a distance from each other of at least three times the transmission line width. coupled microstr ip transmission lines, such as differential signal pairs, must be placed close to each other and maintain the same separation distance throughout the board (separation distance of at figure 2-13. loop length matching for differential traces
product specifications 210xx-dsh-001-d mindspeed technologies? 44 mindspeed proprietary and confidential most twice the trace-width). for buried stripline transmission lines, it is good design practice to maintain equal dis - tance between the conductor and the ground plane on both sides. during pcb manufacturing, over- and under-etching of tr aces used for transmission lines results in impedance dis - continuities. use of wide traces for transmission lines will reduce the impact of etching issues. wide traces also help compensate for skin-effect losses in transmission lines. it should be noted, however, that the wider the traces in a differential pair, the thicker the underlying dielectric layer needs to be. surface mount connectors are preferred over through-mount connectors. connectors should be selected that have controlled characteristic impedances that match the ch aracteristic impedances of the transmission lines.
210xx-dsh-001-d mindspeed technologies? 45 mindspeed proprietary and confidential 3.0 registers table 3-1. register table summary addr register name d7: msb d6 d5 d4 d3 d2 d1 d0: lsb common registers 00h globctrl powerup mspd int mspd int mspd int mspd int mspd int reserved clear_alm 04h refclk_ctrl reserved reserved reserved reserved ref_divr[2] ref_divr[1] ref_divr[0] mspd int 05h mastreset rst rst rst rst rst rst rst rst 06h chipcode chipcode[7] chipcode[6] chipcode[5] chipcode[4] chipcode[3] chipcode[2] chipcode[1] chipcode[0] 07h revcode revcode[7] revcode[6] revcode[5] revcode[4] revcode[3] revcode[2] revcode[1] revcode[0] 10h bistrx_chsel reserved chan[2] chan[1] chan[0] 11h bistrx_ctrl mspd int rx_ctrclr rx_patt[3] rx_patt[2] rx_patt[1] rx_patt[0] en_rx rx_rst 12h bistrx_error err[7] err[6] err[5] err[4] err[3] err[2] err[1] err[0] 14h bisttx_chsel reserved reserved reserved reserved mspd int mspd int tx_chan_1 tx_chan_0 15h bisttx_ctrl err_insert rx2txclk tx_patt[3] tx_patt[2] tx_patt[1] tx_patt[0] en_tx tx_rst 17h bisttx_lolctrl tacq_lol[2] tacq_lol[1] tacq_lol[0] narwin_lol[3] narwin_lol[2] narwin_lol[1] narwin_lol[0] widwin_lol 18h bisttx_pll_ctrla softreset mspd int reserved mspd int reserved mspd int reserved mspd int 19h bisttx_pll_ctrlb pllmode[1] pllmode[0] mspd int mspd int data_rate[3] data_rate[2] data_rate[1] data_rate[0] 1ah bisttx_pll_ctrlc vco_divr[7] vco_divr[6] vco_divr[5] vco_divr[4] vco_divr[3] vco_divr[2] vco_divr[1] vco_divr[0] 1bh bist_pattern0 pattern[19] pattern[18] pattern[17] pattern[16] 1ch bist_pattern1 pattern[15] pattern[14] pattern[13] pattern[12] pattern[11] pattern[10] pattern[9] pattern[8] 1dh bist_pattern2 pattern[7] pattern[6] pattern[5] pattern[4] pattern[3] pattern[2] pattern[1] pattern[0] 1fh bisttx_alarm tx_lol reserved reserved mspd int mspd int mspd int mspd int mspd int 20h temp_mon reserved reserved en_temp_mon strobe_temp 21h temp_value temp[3] temp[2] temp[1] temp[0] 30h alarm_lol mspd int mspd int mspd int mspd int lol_3 lol_2 lol_1 lol_0 31h alarm_loa mspd int mspd int mspd int mspd int loa_3 loa_2 loa_1 loa_0 per channel registers (n = channel/cdr#, m = n+4) m0h cdr_ctrla _n softreset mspd int inh_force mspd int autoinh_en mspd int loa_en mspd int m1h cdr_ctrlb _n cdrmode[1] cdrmode[0] mspd int reserved data_rate[3] data_rate[2] data_rate[1] data_rate[0] m2h cdr_ctrlc _n vco_divr[7] vco_divr[6] vco_divr[5] vco_divr[4] vco_divr[3] vco_divr[2] vco_divr[1] vco_divr[0] m3h out_ctrl _n outlvl[1] outlvl[0] reserved reserved data_pol_flip dataout_en clkout_en clk_pol_flip m4h preemp_ctrl _n reserved mspd int mspd int mspd int mspd int preemph[2] preemph[1] preemph[0] m5h ineq_ctrl _n reserved mspd int mspd int en_dcservo mspd int in_eq[2] in_eq[1] in_eq[0] m6h phadj_ctrl _n i_trim[1] i_trim[0] r_sel[1] r_sel[0] phase_adj[3] phase_adj[2] phase_adj[1] phase_adj[0] m9h lol_ctrl _n tacq_lol[2] tacq_lol[1] tacq_lol[0] narwin_lol[3] narwin_lol[2] narwin_lol[1] narwin_lol[0] widwin_lol mah jitter_reduc _n mspd int mspd int lowjitter mspd int mspd int mspd int mspd int mspd int notes: 1. n = 0 for channel/cdr 0, n = 1 for channel/cdr 1,.., n = 3 for channel/cdr 3. 2. m = 4 for channel/cdr 0, m = 5 for channel/cdr 1,..., m = 7 for channel/cdr 3. for example channel/cdr 0 starts at address 40 h, channel/ cdr 1 at 50h, channel/cdr 2 at 60h, channel/cdr 3 at 70h.
registers 210xx-dsh-001-d mindspeed technologies? 46 mindspeed proprietary and confidential 3.1 global control registers nomenclature: 1. reserved bits: bits that exist and reserved for future use by mindspeed. 2. bits not defined and not reserved do not exist. 3. do not write to reserved or undefined bits ? operation not guaranteed. 4. mspd internal: defines an internal function. must always write the default value to mspd internal bits. when in doubt, read back default value after reset. 3.1.1 global control 3.1.2 external reference freq uency divider control (rfd) table 3-2. global control ( globctrl : address 00h) bits type default label description 7 r/w 1b powerup powers up the ic by enabling the current references 1b: power up the ic (chip powerup) 0b: power down the ic 6:2 r/w 00000b mspd internal n/a 1 r/w 0b reserved n/a 0 r/w 0b clear_alm clears the alarm_loa , alarm_lol alarm registers 1b: clear alarms 0b: normal operation - latch alarm bits note : upon writing a 1b to this bit, it clears the registers, and user needs to write a 0b to enable the normal state. table 3-3. external reference frequency divider control (rfd) ( refclk_ctrl : address 04h) bits type default label description 7:4 r/w 0b reserved n/a 3:1 r/w 000b ref_divr sets the divider ratio to scale down refclk to the internal rate for fra/ loa 000b: rfd = 1 001b: rfd = 2 010b: rfd = 4 011b: rfd = 8 100b: rfd = 12 101b: rfd = 16 110b: rfd = 32 0 r/w 0b mspd internal n/a
registers 210xx-dsh-001-d mindspeed technologies? 47 mindspeed proprietary and confidential 3.1.3 master ic reset 3.1.4 ic electronic identification 3.1.5 ic revision code 3.1.6 built in self-test (bis t) receiver channel select table 3-4. master ic reset ( mastreset : address 05h) bits type default label description 7:0 r/w 0b rst same feature as hardware xrst . resets the entire ic aah: reset upon write to this register with aah 00h: normal operation [default] note : all other values are ignored. table 3-5. ic electronic id ( chipcode : address 06h) bits type default label description 7:0 r 12h chipcode this register contains the identification of this ic. note : for m21011 default is 11h, and for M21001 default is 10h. table 3-6. ic revision code ( revcode : address 07h) bits type default label description 7:0 r 20h revcode this register contains th e revision of the ic. table 3-7. built in self-test (bist) receiver channel select ( bistrx_chsel : address 10h) bits type default label description 7:3 r/w 0b reserved n/a 2:0 r/w 000b chan selects which cdr to route into the bist receiver (active when bistrx_ctrl [1] = 1) 000b: output cdr 0 to bist 001b: output cdr 1 to bist 010b: output cdr 2 to bist 011b: output cdr 3 to bist
registers 210xx-dsh-001-d mindspeed technologies? 48 mindspeed proprietary and confidential 3.1.7 built in self-test (bist) receiver main control register 3.1.8 built in self-test (bist) receiver bit error counter table 3-8. built in self-test (bist) receiver main control register ( bistrx_ctrl : address 11h) bits type default label description 7 r/w 0b mspd internal n/a 6 r/w 0b rx_ctrclr clear the bist rx error count register, bistrx_error (active when bistrx_ctrl [1] = 1) 0b: normal operation 1b: clear register 5:2 r/w 0000b rx_patt selects the bist rx test pattern (active when bistrx_ctrl [1] = 1) 0000b: prbs 2 7 -1 0001b: prbs 2 15 -1 0010b: prbs 2 23 -1 0011b: prbs 2 31 -1 0100b: fibre channel cjtpat 0101b: fibre channel crpat 0110b: 8b/10b countdown pattern 0111b: 16 bit user programmable pattern 1000b: 20 bit user programmable pattern 1 r/w 0b en_rx powers up the bist rx 0b: power down 1b: power up and enable 0 r/w 1b rx_rst resets the bist rx (recommended af ter powerup/enable, active when bistrx_ctrl [1] = 1) 0b: normal bist rx operation 1b: reset of bist rx table 3-9. built in self-test (bist) receiver bit error counter ( bistrx_error : address 12h) bits type default label description 7:0 r/w 00h err bit error count (active when bistrx_ctrl [1] = 1) this register is set to 00h upon reset, and is incremented for every bit error the bist rx receives, up to ffh . at ffh, the register will stay at this level until cleared.
registers 210xx-dsh-001-d mindspeed technologies? 49 mindspeed proprietary and confidential 3.1.9 built in self-test (bis t) transmitter channel select 3.1.10 built in self-test (bist) transmitter main control register table 3-10. built in self-test (bist) transmitter channel select ( bisttx_chsel : address 14h) bits type default label description 7:4 r/w 0000b reserved n/a 3:2 r/w 00b mspd internal n/a 1:0 r/w 00b tx_chan selects which output channel the bi st tx outputs the test pattern on (active when bisttx_ctrl [1] = 1) bit map: 1b = bist tx on, 0b = bist tx off [1]: output channel 1 [0]: output channel 0 note : registers are set up to allow for multicasting bist tx output. table 3-11. built in self-test (bist) transmitter main control register ( bisttx_ctrl : address 15h) bits type default label description 7 r/w 0b err_insert inserts a single bit error into the prbs tx 1b: insert error 0b: normal operation note: setting the register high allows one error to be inserted into the data stream. to insert another error, the user needs to clear, then set this register bit. 6 r/w 0b rx2txclk selects the source of the clock for the bist tx pll (active when bisttx_ctrl [1] = 1) 0b: external reference frequency 1b: recovered clock from bist rx note: for the recovered clock option, th e bist rx must be enabled with bistrx_ctrl [1] = 1, and use the recovered clock from the same cdr selected by bist rx. this option only works for the full-rate case. 5:2 r/w 0000b tx_patt selects the bist tx test pattern (active when bisttx_ctrl [1] = 1) 0000b: prbs 2 7 -1 0001b: prbs 2 15 -1 0010b: prbs 2 23 -1 0011b: prbs 2 31 -1 0100b: fibre channel cjtpat 0101b: fibre channel crpat 0110b: 8b/10b countdown pattern 0111b: 16 bit user programmable pattern 1000b: 20 bit user programmable pattern 1 r/w 0b en_tx powers up the bist tx and pll 0b: power down 1b: power up and enable 0 r/w 1b tx_rst resets the bist tx (recommended af ter powerup/enable; active when bisttx_ctrl [1] = 1) 0b: normal bist tx operation 1b: reset of bist tx
registers 210xx-dsh-001-d mindspeed technologies? 50 mindspeed proprietary and confidential 3.1.11 built in self-test (bist) trans mitter pll loss of lock register table 3-12. built in self-test (bist) transmitter pll loss of lock register ( bisttx_lolctrl : address 17h) (1 of 2) bits type default label description 7:5 r/w 101b tacq_lol sets the value for the lol reference window code 000b 001b 010b 011b 100b 101b 110b 111b value 128 256 512 1024 2048 4096 8192 16384 4:1 r/w 0011b narwin_lol sets the narrow lol window for the lol = h to lol = l transition (transition to in lock threshold) code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b value 2 3 4 6 8 12 16 24 9 10 11 12 13 14 15 32
registers 210xx-dsh-001-d mindspeed technologies? 51 mindspeed proprietary and confidential 3.1.12 built in self-test (bist) tr ansmitter pll cont rol register a 0 r/w 0b widwin_lol sets the wide lol window for the lol = l to lol = h transition (transition to out of lock threshold) narrow code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b wide code 0b 3 4 6 8 12 16 24 32 12 12 12 16 16 16 16 32 wide code 1b 8 12 16 24 32 32 32 32 32 32 32 32 32 32 32 32 table 3-13. built in self-test (bist) transmitter pll control register a ( bisttx_pll_ctrla : address 18h) bits type default label description 7 r/w 0b softreset resets the bist transmitter pll (assuming bisttx_ctrl [1] = 1b) 0b: normal operation 1b: reset pll only 6 r/w 0b mspd internal n/a 5 r/w 0b reserved n/a 4 r/w 0b mspd internal n/a 3 r/w 0b reserved n/a 2 r/w 1b mspd internal n/a 1 r/w 0b reserved n/a 0 r/w 1b mspd internal n/a table 3-12. built in self-test (bist) transmitter pll loss of lock register ( bisttx_lolctrl : address 17h) (2 of 2) bits type default label description
registers 210xx-dsh-001-d mindspeed technologies? 52 mindspeed proprietary and confidential 3.1.13 built in self-test (bist) tr ansmitter pll cont rol register b 3.1.14 built in self-test (bist) tr ansmitter pll cont rol register c 3.1.15 built in self-test (b ist) transmitter 20 bit us er programmable pattern table 3-14. built in self-test (bist) transmitter pll control register b ( bisttx_pll_ctrlb : address 19h) bits type default label description 7:6 r/w 00b pllmode determines state of the pll. must be enabled in addition to the bist tx ( bisttx_ctrl [1] = 1b) 00b: channel active, pll powered up 11b: channel active, pll powered down 5:4 r/w 01b mspd internal n/a 3:0 r/w 0000b data_rate data-rate divider (drd): this divi des down the vco frequency to the desired data-rate 0000b: drd = 1 0001b: drd = 2 0010b: drd = 4 0011b: drd = 8 0100b: drd = 12 0101b: drd = 16 0110b: drd = 24 0111b: drd = 32 1000b: drd = 48 note : please consult f vco,max and f vco,min to determine the frequency range of each drd ratio. table 3-15. built in self-test (bist) transmitter pll control register c ( bisttx_pll_ctrlc : address 1ah) bits type default label description 7:0 r/w 10000000b vco_divr vco comparison divider (vcd): this divider divides down the vco to compare it with the divided down re ference, for use in the fra mode. binary value reflects the divider ratio 01h: minimum value (vcd = 1) . . . ffh: maximum value (vcd = 255) table 3-16. built in self-test (bist) transmitter 20 bit user programmable pattern ( bist_pattern0 : address 1bh) bits type default label description 3:0 r/w 1100b pattern sets the 20 bit user programmable pattern used in the bist [3] msb : pattern bit#19 [2] : pattern bit#18 [1] : pattern bit#17 [0] lsb : pattern bit#16
registers 210xx-dsh-001-d mindspeed technologies? 53 mindspeed proprietary and confidential 3.1.16 built in self-test (b ist) transmitter 16/20 bit user programmable pattern 3.1.17 built in self-test (b ist) transmitter 16/20 bit user programmable pattern 3.1.18 built in self-test (bist) transmitter alarm table 3-17. built in self-test (bist) transmitter 16/20 bit user programmable pattern ( bist_pattern1 : address 1ch) bits type default label description 7:0 r/w 11001100b pattern sets the 16/20 bit user programmable pattern used in the bist [7] msb : pattern bit#15 [6] : pattern bit#14 [5] : pattern bit#13 [4] : pattern bit#12 [3] : pattern bit#11 [2] : pattern bit#10 [1] : pattern bit#9 [0] lsb : pattern bit#8 table 3-18. built in self-test (bist) transmitter 16/20 bit user programmable pattern ( bist_pattern2 : address 1dh) bits type default label description 7:0 r/w 11001100b pattern sets the 16/20 bit user programmable pattern used in the bist [7] msb : pattern bit#7 [6] : pattern bit#6 [5] : pattern bit#5 [4] : pattern bit#4 [3] : pattern bit#3 [2] : pattern bit#2 [1] : pattern bit#1 [0] lsb : pattern bit#0 table 3-19. built in self-test (bist) transmitter alarm ( bisttx_alarm : address 1fh) bits type default label description 7 r 0b tx_lol loss of lock for the bist tx pll (active when bisttx_ctrl [1] = 1) 0b: normal operation 1b: loss of lock 6:5 r/w 00b reserved n/a 4:0 r/w 00000b mspd internal n/a
registers 210xx-dsh-001-d mindspeed technologies? 54 mindspeed proprietary and confidential 3.1.19 internal junctio n temperature monitor 3.1.20 internal junctio n temperature value table 3-20. internal junction temperature monitor ( temp_mon : address 20h) bits type default label description 3:2 r/w 00b reserved n/a 1 r/w 0b en_temp_mon power up and enable the temperature monitor 1b: power up and enable temperature monitor 0b: disable temperature monitor 0 r/w 0b strobe_temp strobes adc for temperature measurement 1b: read temperature 0b: ok to read temperature note : to strobe adc, a rising edge should be provided by writing 1b, then writing 0b to return to default state. table 3-21. internal junction temperature value ( temp_value : address 21h) bits type default label description 3:0 r n/a temp a read of these bits returns the temp erature from the l ast write cycle (to strobe_temp) junction temperature t j 130 c 130 c > t j 120 c 120 c > t j 110 c 110 c > t j 100 c 100 c > t j 90 c 90 c > t j 80 c 80 c > t j 10 c 10 c > t j 0 c 0 c > t j -10 c -10 c > t j -20 c -20 c > t j -30 c -30 c > t j -40 c -40 c > t j temp 1100b 1011b 1010b 1001b 1000b 0111b 0110b 0101b 0100b 0011b 0010b 0001b 0000b condition high-alarm high-alarm high-warning normal normal normal normal normal normal normal low-warning low-alarm low-alarm
registers 210xx-dsh-001-d mindspeed technologies? 55 mindspeed proprietary and confidential 3.1.21 cdr loss of lock register alarm status 3.1.22 loss of activity register alarm status table 3-22. cdr loss of lock register alarm status ( alarm_lol : address 30h) bits type default label description 7:4 r/w 0000b mspd internal n/a 3:0 r n/a lol latched loss of lock alarm status 1b = loss of cdr lock, 0b = normal operation [3]: cdr 3 [2]: cdr 2 [1]: cdr 1 [0]: cdr 0 note: after a clear ( globctrl [0] = 1), this register is cleared and will latch any new alarms that make a l to h transition, and set any pre- existing alarm conditions to h. table 3-23. loss of activity register alarm status ( alarm_loa : address 31h) bits type default label description 7:4 r/w 0000b mspd internal n/a 3:0 r n/a loa latched loss of activity alarm status 1b = loss of input signal, 0b = normal operation [3]: channel 3 [2]: channel 2 [1]: channel 1 [0]: channel 0 note: after a clear ( globctrl [0] = 1), this register is cleared and will latch any new alarms that make a l to h transition, and set any pre- existing alarm conditions to h.
registers 210xx-dsh-001-d mindspeed technologies? 56 mindspeed proprietary and confidential 3.2 individual channel/cdr control multiple instance nomenclature 1. n = 0 for channel/cdr 0, n = 1 for channel/cdr 1,.., n = 3 for channel/cdr 3. 2. m = 4 for channel/cdr 0, m = 5 for channel/cdr 1,.., m = 7 for channel/cdr 3. for example channel/cdr 0 starts at address 40h, channel/cdr 1 at 50h, channel/cdr 2 at 60h, channel/cdr 3 at 70h. 3.2.1 cdr n control register a table 3-24. cdr n control register a ( cdr_ctrla _n: address m0h) bits type default label description 7 r/w 0b softreset resets individual cdr n (setup regist ers remain unchanged; need to softreset after data-rate change) 0b: normal operation 1b: reset single cdr only 6 r/w 0b mspd internal n/a 5 r/w 0b inh_force manual control of the output inhibit if cdr_ctrla _n [3] = 0 0b: normal operation 1b: forced inhibit 4 r/w 0b mspd internal n/a 3 r/w 1b autoinh_en auto inhibit of the output ( doutp = h, doutn = l) if cdr n has a lol or loa condition 0b: auto inhibit disabled, cdr_ctrla _n [5] determines inhibit force state 1b: auto inhibit enabled 2 r/w 1b mspd internal n/a 1 r/w 1b loa_en enables the transition density based lo ss of activity detector for channel n 0b: disable and power down loa circuit 1b: enable loa circuit 0 r/w 1b mspd internal n/a
registers 210xx-dsh-001-d mindspeed technologies? 57 mindspeed proprietary and confidential 3.2.2 cdr n control register b 3.2.3 cdr n control register c table 3-25. cdr n control register b ( cdr_ctrlb _n: address m1h) bits type default label description 7:6 r/w 00b cdrmode determines state of the pll 00b: cdr powered up and active 01b: cdr powered up and bypassed 10b: cdr powered down (no signal through) 11b: cdr powered down and bypassed 5 r/w 0b mspd internal n/a 4 r/w 0b reserved n/a 3:0 r/w 0000b data_rate data-rate divider (drd): this divi des down the vco frequency to the desired data-rate to match input data-rate 0000b: drd = 1 0001b: drd = 2 0010b: drd = 4 0011b: drd = 8 0100b: drd = 12 0101b: drd = 16 0110b: drd = 24 0111b: drd = 32 1000b: drd = 48 note: please consult f vco,max and f vco,min to determine frequency range of each drd ratio. table 3-26. cdr n control register c ( cdr_ctrlc _n: address m2h) bits type default label description 7:0 r/w 10000000b vco_divr vco comparison divider (vcd): this divides down the vco, to compare it with the scaled reference clock, for use in the fra/loa mode. binary value reflects the divider ratio 1h: minimum value (vcd = 1) . . . ffh: maximum value (vcd = 255)
registers 210xx-dsh-001-d mindspeed technologies? 58 mindspeed proprietary and confidential 3.2.4 output buffer control for cdr n 3.2.5 output buffer pre-empha sis control for output n table 3-27. output buffer control for cdr n ( out_ctrl _n: address m3h) bits type default label description 7:6 r/w 10b outlvl determines the output swing of a data and/or clock buffer for cdr n in pcml mode: 00b: power down 01b: 600 mv 10b: 1v 11b: 1.3v for lvds, the output swing is reduced to: 00b: power down 01b: rrl 450 mv 10b: gpl 650 mv 11b: 1v for pcml+, the output swing is increased to: 00b: power down 01b: 1v 10b: 1.3v 11b: 1.6v 5:4 r/w 00b reserved n/a 3 r/w 0b data_pol_flip flips the polarity of the output data 0b: normal 1b: polarity flip 2 r/w 1b dataout_en enables the data output driver n 1b: data output enabled to level specified in out_ctrl _n [7:6] 0b: data output disabled and powered down 1 r/w 0b clkout_en enables the clock output driver n 1b: clock output enabled to level specified in out_ctrl _n [7:6] 0b: clock output disabled and powered down 0 r/w 0b clk_pol_flip flips the polarity of the output clock 0b: normal 1b: polarity flip table 3-28. output buffer pre-emphasis control for output n ( preemp_ctrl _n: address m4h) bits type default label description 7 r/w 0b reserved n/a 6:3 r/w 1000b mspd internal n/a 2:0 r/w 000b preemph selects the digital pre-emphasis level 111b: 200% 110b: 150% 101b: 100% 100b: 75% 011b: 50% 010b: 37.5% 001b: 25% 000b: pre-emphasis off
registers 210xx-dsh-001-d mindspeed technologies? 59 mindspeed proprietary and confidential 3.2.6 input equalization control for output n table 3-29. input equalization control for output n ( ineq_ctrl _n: address m5h) bits type default label description 7 r/w 0b reserved n/a 6:5 r/w 00b mspd internal n/a 4 r/w 1b en_dcservo enables dc servo in the input channel to remove offset based deterministic jitter 0b: dc servo d j attenuator off 1b: dc servo d j attenuator on 3 r/w 0b mspd internal n/a 2:0 r/w 000b in_eq selects the input equalization level 111b: maximum input equalization level . . . 100b: nominal input equalization level . . . 001b: minimum input equalization level 000b: input equalization disabled note: the 100b setting is optimized for pcb trace lengths between 10 - 46 inches, although other settings may be optimal for some applications.
registers 210xx-dsh-001-d mindspeed technologies? 60 mindspeed proprietary and confidential 3.2.7 cdr n loop bandwidth an d data sampling point adjust 3.2.8 cdr n fra lol window control table 3-30. cdr n loop bandwidth and data sampling point adjust ( phadj_ctrl _n: address m6h) bits type default label description 7:6 r/w 10b i_trim adjusts the charge-pump current; the loop bandwidth (f lbw ) scales proportionately 00b: 0.65x 01b: 0.8x 10b: nominal 11b: 1.15x 5:4 r/w 01b r_sel adjusts the resistor of the cdr loop filter; the loop bandwidth (f lbw ) scales proportionately 00b: 80% of the nominal value 01b: nominal 10b: 4x nominal value 3:0 r/w 0000b phase_adj adjusts the static phase offset (sampling point) of the data 1111b: -122.5 mui 1110b: -105 mui 1101b: -87.5 mui 1100b: -70 mui 1011b: -52.5 mui 1010b: -35.0 mui 1001b: -17.5 mui 1000b: 0 mui 0000b: 0 mui 0001b: 17.5 mui 0010b: 35.0 mui 0011b: 52.5 mui 0100b: 70.0 mui 0101b: 87.5 mui 0110b: 105 mui 0111b: 122.5 mui table 3-31. cdr n fra lol window control ( lol_ctrl _n: address m9h) (1 of 2) bits type default label description 7:5 r/w 101b tacq_lol sets the value for the lol reference window code 000b 001b 010b 011b 100b 101b 110b 111b value 128 256 512 1024 2048 4096 8192 16384
registers 210xx-dsh-001-d mindspeed technologies? 61 mindspeed proprietary and confidential 4:1 r/w 0100b narwin_lol sets the narrow lol window for the lol = h to lol = l transition (transition to in lock threshold) code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b value 2 3 4 6 8 12 16 24 9 10 11 12 13 14 15 32 0 r/w 0b widwin_lol sets the wide lol window for the lol = l to lol = h transition (transition to out of lock threshold) narrow code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b wide code 0b 3 4 6 8 12 16 24 32 12 12 12 16 16 16 16 32 wide code 1b 8 12 16 24 32 32 32 32 32 32 32 32 32 32 32 32 table 3-31. cdr n fra lol window control ( lol_ctrl _n: address m9h) (2 of 2) bits type default label description
registers 210xx-dsh-001-d mindspeed technologies? 62 mindspeed proprietary and confidential 3.2.9 jitter reduction control table 3-32. jitter reduction control ( jitter_reduc _n: address mah) bits type default label description 7:6 r/w 01b mspd internal n/a 5 r/w 0b lowjitter when data-rate is in the range (2 .45 gbps - 2.55 gbps)/drd, setting this bit to 1b will reduce output jitter (drd is data-rate divider). 1b: reduce output jitter 0b: normal operation note: this bit should be set to 1b for sonet sts-n, and gigabit ethernet applications. 4:0 r/w mspd internal any value may be written to this re gister with no effect on performance.
210xx-dsh-001-d mindspeed technologies? 63 mindspeed proprietary and confidential 4.0 appendices 4.1 glossary of terms/acronyms ta bl e 4-1 contains a list of acronyms used in this data sheet. table 4-1. acronyms ber bit-error rate bist built-in self test cdr clock and data recovery array drd data-rate divider evm evaluation module fll frequency lock loop fra frequency reference acquisition ie input equalizer isi inter-symbol interference loa loss of activity lol loss of lock lolcir loss of lock circuitry mlf microleadframe nrw narrow reference window pcb printed circuit board pll phase lock loop rfd reference frequency divider sonet synchronous optical network vcd vco comparison divider wrw wide reference window xpts crosspoint switch
appendices 210xx-dsh-001-d mindspeed technologies? 64 mindspeed proprietary and confidential 4.2 reference documents 4.2.1 external the following external documents were referenced in this data sheet. synchronous optical network (sonet) transport systems: common generic criteria gr-253-core the i 2 c bus specification version 2.1 fibre channel - methodologies for jitter and si gnal quality specification - mjsq & fc-pi-2 application notes for surface mount assembly of amkor?s microleadframe (mlf) packages amkor technology thermal test report tt-00-06 4.2.2 mindspeed the following mindspeed documents were referenced in this data sheet. m21012/m21011/M21001 evaluation module user guide jitter tolerance and generation of mindspeed technologies crosspoint switches and clock & data recovery arrays
210xx-dsh-001-d mindspeed technologies? 65 mindspeed proprietary and confidential ? 2005, mindspeed technologies tm , inc. all rights reserved. information in this document is provided in connection with mindspeed technologies tm ("mindspeed tm ") products. these materials are provided by mindspeed as a service to its customers and may be used for informational pur- poses only. except as provided in mindspeed?s terms and conditions of sale for such products or in any separate agreement related to this document, mindspeed assumes no liability whatsoever. mindspeed assumes no respon- sibility for errors or omissions in these materials. mi ndspeed may make changes to specifications and product descriptions at any time, without notice. mindspeed makes no commitment to update the information and shall have no responsibility whatsoever for co nflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" without warranty of any kind, either express or implied, relating to sale and/or use of mindspeed products including liability or war- ranties relating to fitness for a particular purpose, consequential or incidental dam- ages, merchantability, or infringement of any patent, copyright or other intellectual property right. mindspeed further does not warrant the accuracy or completeness of the information, text, graphics or ot her items contained within these materials. mindspeed shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. mindspeed products are not intended for use in medical, lifesaving or life sustaining applications. mindspeed cus- tomers using or selling mindspeed products for use in such applications do so at their own risk and agree to fully indemnify mindspeed for any damages resulting from such improper use or sale.
210xx-dsh-001-d mindspeed technologies? 66 mindspeed proprietary and confidential www.mindspeed.com general information: (949) 579-3000 headquarters - newport beach 4000 macarthur blvd., east tower newport beach, ca. 92660

▲Up To Search▲

Price & Availability of M21001

	To Download M21001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .